PM0214 datasheet(98/245 Pages) STMICROELECTRONICS

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The STM32 Cortex-M4 instruction set

PM0214

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DocID022708 Rev 4

; Adds top halfword of R3 with bottom halfword of R2 and

; writes to top halfword of R7.

3.5.15

TST and TEQ

Test bits and test equivalence.

Syntax

TST{cond} Rn, Operand2

TEQ{cond} Rn, Operand2

where:

•

‘cond’ is an optional condition code (see Conditional execution on page 64)

•

‘Rn’ is the register holding the first operand

•

‘Operand2’ is a flexible second operand (see Flexible second operand on page 59) for

details of the options.

Operation

These instructions test the value in a register against operand2. They update the condition

flags based on the result, but do not write the result to a register.

The TST instruction performs a bitwise AND operation on the value in Rn and the value of

operand2. This is the same as the ANDS instruction, except that it discards the result.

To test whether a bit of Rn is 0 or 1, use the TST instruction with an operand2 constant that

has that bit set to 1 and all other bits cleared to 0.

The TEQ instruction performs a bitwise exclusive OR operation on the value in Rn and the

value of operand2. This is the same as the EORS instruction, except that it discards the

result.

Use the TEQ instruction to test if two values are equal without affecting the V or C flags.

TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the

logical exclusive OR of the sign bits of the two operands.

Restrictions

Do not use either SP or PC.

Condition flags

These instructions:

•

Update the N and Z flags according to the result

•

Can update the C flag during the calculation of operand2 (see Flexible second operand

on page 59).

•

Do not affect the V flag

Examples

TST R0, #0x3F8

; perform bitwise AND of R0 value to 0x3F8,

; APSR is updated but result is discarded

TEQEQ R10, R9

; conditionally test if value in R10 is equal to

; value in R9, APSR is updated but result is discarded

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