AN3427 datasheet(49/52 Pages) STMICROELECTRONICS

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AN3427

Firmware migration using the library

Doc ID 019001 Rev 1

49/52

4.8

Backup data registers

In STM32 F1 series the Backup data registers are managed through the BKP peripheral,

while in F2 series they are a part of the RTC peripheral (there is no BKP peripheral).

The example below shows how to write to/read from Backup data registers in STM32 F1

series:

uint16_t BKPdata = 0;

...

/* Enable APB2 interface clock for PWR and BKP */

RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);

/* Enable write access to Backup domain */

PWR_BackupAccessCmd(ENABLE);

/* Write data to Backup data register 1 */

BKP_WriteBackupRegister(BKP_DR1, 0x3210);

/* Read data from Backup data register 1 */

BKPdata = BKP_ReadBackupRegister(BKP_DR1);

In F2 series you have to update this code as follows:

uint16_t BKPdata = 0;

...

/* PWR Clock Enable */

RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);

/* Enable write access to Backup domain */

PWR_RTCAccessCmd(ENABLE);

/* Write data to Backup data register 1 */

RTC_WriteBackupRegister(RTC_BKP_DR1, 0x3220);

/* Read data from Backup data register 1 */

BKPdata = RTC_ReadBackupRegister(RTC_BKP_DR1);

The main changes in the source code in F2 series vs. F1 are described below:

There is no BKP peripheral

Write to/read from Backup data registers are done through RTC driver

Backup data registers naming changed from BKP_DRx to RTC_BKP_DRx, and

numbering starts from 0 instead of 1

4.9

Miscellaneous

4.9.1

Ethernet PHY interface selection

In STM32 F1 series the Ethernet PHY interface selection is made in the AFIO peripheral,

while in F2 series this configuration is made in the SYSCFG peripheral.

The example below shows how to configure the Ethernet PHY interface in STM32 F1 series:

/* Configure Ethernet MAC for connection with an MII PHY */

GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);

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