AN3427 datasheet(35/52 Pages) STMICROELECTRONICS

35 / 52 page

AN3427

Peripheral migration

Doc ID 019001 Rev 1

35/52

3.10

PWR

In STM32 F2 series the PWR controller presents some differences vs. F1 series, these

differences are summarized in the table below. However, the programming interface is

unchanged.

Table 12.

PWR differences between STM32 F1 series and STM32 F2 series

PWR

STM32 F1 series

STM32 F2 series

Power supplies

1. VDD = 2.0 to 3.6 V: external power

supply for I/Os and the internal

regulator. Provided externally through

VDD pins.

1. VDD = 1.8 to 3.6 V: external power supply for I/Os

and the internal regulator (when enabled), provided

externally through VDD pins. On WLCSP package, VDD

ranges from 1.65 to 3.6 V.

VDD/VDDA minimum value of 1.65 V is obtained when

the device operates in a reduced temperature range.

2. VSSA, VDDA = 2.0 to 3.6 V: external

analog power supplies for ADC, DAC,

Reset blocks, RCs and PLL (minimum

voltage to be applied to VDDA is 2.4 V

when the ADC or DAC is used). VDDA

and VSSA must be connected to VDD

and VSS, respectively.

2. VSSA, VDDA = 1.8 to 3.6 V: external analog power

supplies for ADC, DAC, Reset blocks, RCs and PLL.

VDDA and VSSA must be connected to VDD and VSS,

respectively.

3. VBAT = 1.8 to 3.6 V: power supply for

RTC, external clock 32 kHz oscillator

and backup registers (through power

switch) when VDD is not present.

3. VBAT = 1.65 to 3.6 V: power supply for RTC, external

clock 32 kHz oscillator and backup registers (through

power switch) when VDD is not present.

Note: in UFBGA and WLCSP packages, the internal

regulator can be switched off

Battery backup

domain

– Backup registers

–RTC

–LSE

– PC13 to PC15 I/Os

Note: in F1 series the Backup registers

are integrated in the BKP peripheral.

– RTC with backup registers

–LSE

– PC13 to PC15 I/Os, plus PI8 I/O (when available)

Note: in F2 series the backup registers are integrated in

the RTC peripheral

4 Kbytes backup SRAM when the low power backup

regulator is enabled (this SRAM can be used as

EEPROM as long as the VBAT supply is present)

Power supply

supervisor

Integrated POR / PDR circuitry

Programmable Voltage Detector (PVD)

Integrated POR / PDR circuitry

Programmable voltage detector (PVD)

Brownout reset (BOR)

Low-power

modes

Sleep mode

Stop mode

Standby mode (1.8V domain powered-

off)

Sleep mode + peripherals automatic clock gating(*)

Stop mode

Standby mode (1.2 V domain powered off)

(*)To further reduce power consumption in Sleep mode

the peripheral clocks can be disabled prior to executing

the WFI or WFE instructions.

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