AN3427 datasheet(20/52 Pages) STMICROELECTRONICS

20 / 52 page

Peripheral migration

AN3427

20/52

Doc ID 019001 Rev 1

Peripheral access configuration: The address mapping of some peripherals has been

changed in F2 series vs. F1 series, so you need to use different registers to

[enable/disable] or [enter/exit] the peripheral [clock] or [from reset mode].

Table 5.

Example of migrating system clock configuration code from F1 to F2 series

STM32F105/7 running at 72 MHz (PLL as clock

source) with 2 wait state

STM32F2xx running at 120 MHz (PLL as clock

source) with 3 wait state

/* Enable HSE ----------------------------*/

RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */

while((RCC->CR & RCC_CR_HSERDY) == 0)

{

}

/* Flash configuration -------------------*/

/* Prefetch ON, Flash 2 wait state */

FLASH->ACR |= FLASH_ACR_PRFTBE |

FLASH_ACR_LATENCY_2;

/* AHB and APBs prescaler configuration --*/

/* HCLK = SYSCLK */

RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */

RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */

RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

/* PLLs

configuration -------------------*/

/* PLL2CLK = (HSE / 5) * 8 = 40 MHz

PREDIV1CLK = PLL2 / 5 = 8 MHz */

RCC->CFGR2 |= RCC_CFGR2_PREDIV2_DIV5 |

RCC_CFGR2_PLL2MUL8 |

RCC_CFGR2_PREDIV1SRC_PLL2 |

RCC_CFGR2_PREDIV1_DIV5;

/* Enable PLL2 */

RCC->CR |= RCC_CR_PLL2ON;

/* Wait till PLL2 is ready */

while((RCC->CR & RCC_CR_PLL2RDY) == 0)

{

}

/* PLLCLK = PREDIV1 * 9 = 72 MHz */

RCC->CFGR |= RCC_CFGR_PLLXTPRE_PREDIV1 |

RCC_CFGR_PLLSRC_PREDIV1 |

RCC_CFGR_PLLMULL9;

/* Enable the main PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till the main PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Main PLL used as system clock source --*/

RCC->CFGR |= RCC_CFGR_SW_PLL;

/* Wait till the main PLL is used as system

clock source */

while ((RCC->CFGR & RCC_CFGR_SWS) !=

RCC_CFGR_SWS_PLL)

{

}

/* Enable HSE ----------------------------*/

RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */

while((RCC->CR & RCC_CR_HSERDY) == 0)

{

}

/* Flash configuration -------------------*/

/* Flash prefetch and cache ON, Flash 3 wait

state */

FLASH->ACR = FLASH_ACR_PRFTEN |

FLASH_ACR_ICEN |

FLASH_ACR_DCEN |

FLASH_ACR_LATENCY_3WS;

/* AHB and APBs prescaler configuration --*/

/* HCLK = SYSCLK */

RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK / 2 */

RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;

/* PCLK1 = HCLK / 4 */

RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;

/* PLL configuration ---------------------*/

PLLCLK = ((HSE / PLL_M) * PLL_N) / PLL_P

= ((25 MHz / 25) * 240) / 2

= 120 MHz */

RCC->PLLCFGR = PLL_M | (PLL_N << 6) |

(((PLL_P >> 1) -1) << 16) |

(RCC_PLLCFGR_PLLSRC_HSE) |

(PLL_Q << 24);

/* Enable the main PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till the main PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Main PLL used as system clock source --*/

RCC->CFGR |= RCC_CFGR_SW_PLL;

/* Wait till the main PLL is used as system

clock source */

while ((RCC->CFGR & RCC_CFGR_SWS ) !=

RCC_CFGR_SWS_PLL);

{

}

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