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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AN3427 датащи(PDF) 22 Page - STMicroelectronics |
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AN3427 датащи(HTML) 22 Page - STMicroelectronics |
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22 / 52 page  Peripheral migration AN3427 22/52 Doc ID 019001 Rev 1 1), finally enable the I2S clock (using RCC_APB1ENR[SPI2EN] or/and RCC_APB1ENR[SPI3EN] bits) To use external clock as I2S clock source: set RCC_CFGR[I2SSRC] bit to 0, then enable the I2S clock (using RCC_APB1ENR[SPI2EN] or/and RCC_APB1ENR[SPI3EN] bits) b) USB OTG FS and SDIO: in the F2 series the USB OTG FS requires a frequency of 48 MHz to work correctly, while the SDIO requires a frequency less than or equal to 48 MHz to work correctly. This clock is derived from the PLL through the Q divider. c) ADC: in the F2 series the ADC features two clock schemes: Clock for the analog circuitry: ADCCLK, common to all ADCs. This clock is generated from the APB2 clock divided by a programmable prescaler that allows the ADC to work at fPCLK2/2, /4, /6 or /8. The maximum value of ADCCLK is 30 MHz when the APB2 clock is at 60 MHz. This configuration is done using ADC_CCR[ADCPRE] bits. Clock for the digital interface (used for register read/write access): This clock is equal to the APB2 clock. The digital interface clock can be enabled/disabled individually for each ADC through the RCC_APB2ENR register (ADC1EN, ADC2EN and ADC3EN bits). However, there is only a single bit (RCC_APB2RSTR[ADCRST]) to reset the three ADCs at the same time. |
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