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AN2784 датащи(PDF) 25 Page - STMicroelectronics

номер детали AN2784
подробное описание детали  Using the high-density STM32F10xxx FSMC peripheral to drive external memories
PDF  31 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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AN2784 датащи(HTML) 25 Page - STMicroelectronics

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AN2784
Interfacing with an 8-bit NAND Flash memory
Doc ID 14779 Rev 4
25/31
Using the above described formulas, the memory timings in Table 7 and the
STM32F10xCDE FSMC asynchronous timings in Table 2, we have:
●
Setup time: 0x0
●
Wait time: 0x2
●
Hold time: 0x1
●
HiZ time: 0x0
4.3
Hardware connection
Table 8 gives the correspondence between the NAND Flash memory pins and the FSMC
pins and shows the GPIO configuration for each FSMC pin.
In case of a 16-bit NAND Flash memory, the data/address bus is 16 bits wide and the
remaining FSMC data/address bus are used.
tRP
Read Enable low to Read Enable high
15
ns
tCS
Chip Enable low to Write Enable high
20
ns
tALS
AL setup time
15
ns
tCLS
CL Setup time
15
ns
tCH
E Hold time
5
ns
tALH
AL Hold time
5
ns
tCLH
CL Hold time
5
ns
tDS
Data Valid to Write Enable high
15
ns
tWC
Write Enable low to Write Enable low
30
ns
tRC
Read Enable low to Read Enable low
30
ns
tREA
Read Enable low to Output Valid
18
ns
Table 7.
NAND512W3A2C Flash memory timings (continued)
Symbol
Parameter
Value
Unit
Table 8.
NAND512W3A signal to FSMC pin correspondence
Memory signals FSMC signals
Pin / Port
assignment
Pin / Port
configuration
Signal description
AL
ALE/A17
PD11
AF push-pull
Address Latch Enable
CL
CLE/A16
PD12
AF push-pull
Command Latch Enable
I/O0-I/O7
D0-D7
Port D/Port E
AF push-pull
Data D0-D7
E
NCE2
PD7
AF push-pull
Chip Enable
R
NOE
PD4
AF push-pull
Output Enable
W
NWE
PD5
AF push-pull
Write Enable
RB
NWAIT/INT2
PD6/PG6
Input pull-up
Ready/Busy signal



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