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AN2784 датащи(PDF) 16 Page - STMicroelectronics |
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AN2784 датащи(HTML) 16 Page - STMicroelectronics |
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16 / 31 page ![]() Interfacing with a nonmultiplexed, asynchronous 16-bit SRAM AN2784 16/31 Doc ID 14779 Rev 4 3 Interfacing with a nonmultiplexed, asynchronous 16- bit SRAM 3.1 FSMC configuration SRAMs and NOR Flash memories share the same FSMC banks. The protocol to be used depends on the selected memory type. To control an SRAM, the FSMC provides the following possible features: ● Enable or disable the address/data multiplexing feature ● Select the memory type to be used: NOR/SRAM/PSRAM ● Define the external memory databus width: 8/16 bits ● Enable or disable the extended mode: this mode is used to access the memory with a different timing configuration for read and write operations. Like for NOR Flash memories, the user has to compute and set the following parameters as a function of the information in the SRAM datasheet: ADDSET: address setup time DATAST: data setup time Figure 6 and Figure 7 show the different timings for a typical SRAM access. Figure 6. SRAM asynchronous read access timing A[25:0] NOE (ADDSET +1) (DATAST + 1) Memory transaction Data strobe NEx D[15:0] HCLK cycles HCLK cycles NWE NBL[1:0] data driven by memory ai14720c High 2 HCLK cycles Data sampled |
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