AN2784 datasheet(18/31 Pages) STMICROELECTRONICS

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Interfacing with a nonmultiplexed, asynchronous 16-bit SRAM

AN2784

18/31

Doc ID 14779 Rev 4

Hence the following equations:

((ADDSET + 1) + (DATAST + 1)) × tHCLK  max (tWC)

DATAST × tHCLK = tPWE1

For read access, DATAST must verify:

DATAST

 (t

AA + tsu(Data_NE) + tv(A_NE))/tHCLK – ADDSET – 4

Table 5 gives the meanings and values of the SRAM parameters.

Using the above described formulas, the memory timings in Table 5 and the

STM32F10xCDE FSMC asynchronous timings in Table 2, we have:

●

Address setup time: 0x0

●

Data setup time: 0x1

3.3

Hardware connection

Table 6 gives the correspondence between SRAM pins and FSMC pins and shows the

GPIO configuration for each FSMC pin.

In case of an 8-bit SRAM, the data/address bus is 8 bits wide and D8-D15 should not be

connected to the FSMC. The unused FSMC pins can be used as general purpose I/O pins

Figure 8 shows a typical connection between an STM32F10xxx microcontroller and an

IS61WV51216BLL SRAM. It is an abstract from the schematic of the STM32F10xxx

evaluation board: STM3210E-EVAL.

Table 5.

IS61WV51216BL SRAM timings

Symbols

Parameter

Value

Unit

tWC

Write cycle time

tRC

Read cycle time

tPWE1

Write Enable low pulse width

tAA

Address access time

Table 6.

IS61WV51216BLL signal to FSMC pin correspondence

Memory

signals

FSMC

signals

Pin / Port assignment

Pin / Port

configuration

Signal description

A0-A18

Port F/Port G/Port E/Port D

AF push-pull

Address A0-A18

I/O0-I/O15

D0-D15

Port D/Port E

AF push-pull

Data D0-D15

NE3

PG10

AF push-pull

Chip Enable

NOE

PD4

AF push-pull

Output Enable

NWE

PD5

AF push-pull

Write Enable

NBL0

PE0

AF push-pull

Lower byte control

NBL1

PE1

AF push-pull

Upper byte control

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