Interfacing with an 8-bit NAND Flash memory

AN2784

24/31

Doc ID 14779 Rev 4

Based on the NAND Flash memory access timings shown in Figure 4, the following

equations are found:

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The write or read access time is the time between the falling edge and the rising edge

of the NAND Flash memory Chip Select signal. It is computed as a function of the

FSMC timing parameter:

●

The Wait time is measured between the falling edge and the rising edge of the

Write/Read Enable signal:

●

For write access, the HIZ parameter is the time measured between the falling edge of

the Chip Select signal and the data setup on bus:

●

The HOLD timing is given in the NAND datasheet as follows:

High

To make sure of the correct timing configuration of the FSMC, the timings have to take into

consideration:

●

The maximum read/write access time

●

The different internal FSMC delays

●

The different internal memory delays

Hence, we have the following equations following the NAND512W3A NAND datasheet:

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●

●

●

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Considering the different timings in the FSMC and the memory, the equations become:

●

WAIT must verify:

WAIT

Note:

Table 7 gives the meanings and values of the NAND512W3A2C memory parameters.

Table 7.

NAND512W3A2C Flash memory timings

Symbol

Parameter

Value

Unit

Chip Enable low to output valid

35

ns

Write Enable low to Write Enable high

15

ns