AN2784

Interfacing with a nonmultiplexed, asynchronous 16-bit NOR Flash memory

Doc ID 14779 Rev 4

11/31

2.1.1

Typical use of the FSMC to interface with a NOR Flash memory

The STM32F10xxx FSMC has four different banks of 64 Mbytes to support NOR Flash

memories/PSRAMs and similar external memories.

The external memories share the address, data and control signals with the controller. Each

external device is accessed by means of a unique Chip Select signal, but the FSMC

performs only one access at a time to an external device.

Each bank is configured by means of dedicated registers. Configuration includes the

different features and the timing parameters.

In this application note, the M29W128FL memory is used as a reference. The M29W128FL

memory is a 16-bit, asynchronous, nonmultiplexed NOR Flash memory. Based on these

data, the FSMC is configured as follows:

Bank 2 is selected to support the NOR Flash memory device:

●

Bank 2 is enabled: BCR2_MBKEN bit set to ‘1’

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Memory type is NOR: BCR2_MTYP is set to ‘10’ to select the NOR memory type

●

Databus width is 16-bit: BCR2_MWID is set to ‘01’ to select the 16-bit width

●

It is a nonmultiplexed memory: BCR2_MUXEN is reset.

All remaining parameters must be kept cleared.

2.2

Timing computation

As described above, for asynchronous NOR Flash-like memories, there are different

possible access protocols. The first step is therefore to define the kind of protocol that

should be used with the specific memory. The choice depends on the different control

signals and the behavior of the memory during read and write transactions.

In the case of an asynchronous NOR Flash memory, the Mode 2 protocol will be used. If the

used memory can provide an NADV signal, the Extended ModeB protocol should be used.

With the M29W129FL, we will use the Mode2 protocol. We will therefore not use any

extended mode and the timings will be the same for read and write operations. In this case,

the NOR memory controller needs two timing parameters: ADDSET and DATAST.

These parameters are computed according to the NOR Flash memory characteristics and

according to the HCLK clock of the STM32F10xxx.

Based on the NOR Flash memory access timings illustrated in Figure 3 and Figure 4, the

following equations are found:

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The write or read access time is the time between the falling edge and the rising edge

of the memory Chip Select signal. This time is computed as a function of the FSMC

timing parameter:

●

In write operations, the DATAST parameter is measured between the falling edge and

the rising edge of the write signal as follows: