AN2784

Interfacing with a nonmultiplexed, asynchronous 16-bit SRAM

Doc ID 14779 Rev 4

17/31

Figure 7.

SRAM asynchronous write access timing

3.1.1

Typical use of the FSMC to interface with an SRAM

In this application note, the IS61WV51216BLL memory is used as the reference.

The IS61WV51216BLL memory is a nonmultiplexed, asynchronous, 16-bit memory. Bank3

is selected to support the SRAM device. Based on these data, the FSMC is configured as

follows:

●

Bank3 is enabled: BCR3_MBKEN bit set to ‘1’

●

Memory type is SRAM: BCR3_MTYP is set to ‘00’ to select the SRAM memory type

●

Databus width is 16 bits: BCR3_MWID is set to ‘01’ to select the 16-bit width

●

The memory is nonmultiplexed: BCR3_MUXEN is reset

All remaining parameters must be kept cleared.

3.2

Timing computation

The SRAM shares the same banks and configuration register as the NOR Flash memory.

As a result, the timing computation method is the same as described in detail in the NOR

Flash section (Section 2.2: Timing computation on page 11).

The FSMC is configured on the basis of the SRAM access timings illustrated in Figure 6 and

Figure 7, and taking into account the following:

●

the maximum read/write access time

●

the different internal FSMC delays

●

the different internal memory delays

A[25:0]

NOE

(ADDSET +1)

(DATAST + 1)

Memory transaction

NEx

D[15:0]

HCLK cycles

HCLK cycles

NWE

NBL[1:0]

data driven by FSMC

ai14721b

1HCLK