AN3393 datasheet(24/103 Pages) STMICROELECTRONICS

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AN3393

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DocID018750 Rev 4

4.10

PEAK1 (19h), PEAK2 (1Ah)

Peak 1 value for State Machine 1, default value: 00h.

Peak 2 value for State Machine 2, default value: 00h.

The peak register stores the highest absolute peak value detected.

The peak value is reset when the REL command occurs or a new initial start occurs.

The value of the peak counter is expressed in two’s complement.

For more information about peak detection refer to Section 8.

4.11

Vector filter coefficients (1Bh-1Eh)

SYNC1

0 = State Machine 1 running normally, 1 = State Machine 1 stopped and

waiting for restart request from State Machine 2.

SYNC2

0 = State Machine 2 running normally, 1 = State Machine 2 stopped and

waiting for restart request from State Machine 1.

INT_SM1

0 = no interrupt on State Machine 1, 1 = State Machine 1 interrupt occurred.

The interrupt signal is reset when the OUTS1 register is read.

INT_SM2

0 = no interrupt on State Machine 2, 1 = State Machine 2 interrupt occurred.

The interrupt signal is reset when OUTS2 register is read.

DOR

The Data OverRun bit indicates when a new set of data has overwritten the

previous set in the output registers.

0 = no overrun, 1 = data overrun.

The overrun bit is automatically cleared when data are read and no new data

have been produced in the meantime.

DRDY

0 = data not ready, 1 = data ready.

New data are ready in the output registers (refer to Section 2.1).

Table 17. STAT register description (continued)

Bit name

Description

Table 18. PEAK1, 2 register description

Bit

Name

PKx_7

PKx_6

PKx_5

PKx_4

PKx_3

PKx_2

PKx_1

PKx_0

Default

00000000

Table 19. VFC register description

Add

Mnemonic

Definition

Default

1Bh

VFC_1

Coefficient 1

00h

1Ch

VFC_2

Coefficient 2

00h

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