AN3393 datasheet(94/103 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

AN3393

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read the FIFO content at any time because it is maintained unchanged until Bypass mode is

selected. The read is composed of a 32-sample set of 6 bytes for a total of 192 bytes and

retrieves data starting from the oldest sample stored in FIFO (F0). The overrun interrupt and

the OVRN bit are reset when the first sample set has been read. The Bypass mode setting

resets FIFO and allows the user to enable FIFO mode again.

10.3.3

Stream mode

In Stream mode FIFO continues filling and when the buffer is full, the FIFO index restarts

from the beginning and older data is replaced by the current. The oldest values continue to

be overwritten until a read operation frees FIFO slots. Host processor reading speed is most

important in order to free slots faster than new data is made available. FMODE[2:0] Bypass

configuration is used to stop this mode.

Follow these steps for FIFO mode configuration:

Turn on FIFO by setting the FIFO_EN bit to “1” in control register 6 (25h). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are

frozen to the last samples set loaded.

Set overrun or watermark interrupt through P1_OVERRUN and P1_WTM bits in

CTRL_REG6 (25h).

Activate Stream mode by setting the FMODE[2:0] field to “010” in the FIFO control

As described for the FIFO mode, data can be retrieved when the interrupt overrun event

occurs, by performing a 32-sample set read of the output registers. Data can be retrieved

also on the watermark interrupt event, when the application requires a lower number of

samples.

Figure 30. Stream mode fast reading behavior

In Stream mode, the FIFO buffer fills continuously (from F0 to F31) at the selected output

data rate. When the buffer is full, the OVRN flag goes high and the recommended solution is

to read all FIFO samples (192 bytes) faster than 1*ODR in order to free FIFO slots for the

new acceleration data. This allows avoiding loss of data and limits intervention by the host

processor which increases system efficiency. Three different cases can be observed:

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