AN3393 datasheet(96/103 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

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shifted into the output registers in order to allow the next read operation. In the case of a

read slower than 1*ODR, some data can be retrieved from FIFO after which a new sample

is inserted into the addressed location. In Figure 32 the fourth read command starts after the

refresh of the F3 index and this generates a disconnect in the reading of data. The OVRN

flag advises the user that this event has taken place. In this example, three correct samples

have been read, the number of correctly recovered samples is dependent on the difference

between the current ODR and the FIFO sample set reading timeframe.

10.3.4

Stream-to-FIFO mode

This mode is a combination of the Stream and FIFO modes described above. In Stream-to-

FIFO mode, the FIFO buffer starts operating in Stream mode and switches to FIFO mode

when INT2 occurs.

Follow these steps for Stream-to-FIFO mode configuration:

Configure State Machine 2 in order to generate interrupt on INT2.

Turn on FIFO by setting the FIFO_EN bit to “1” in control register 6 (25h). After this

operation the FIFO buffer is enabled but is not collecting data, output registers are

frozen to the last samples set loaded.

Activate Stream-to-FIFO mode by setting the FMODE[2:0] field to “011” in the FIFO

control register (2Eh).

The interrupt trigger is related to the INT_SM2 bit in the STAT (18h) register and it is

generated even if the interrupt signal is not driven to an interrupt pad. A mode switch is

performed if both INT_SM2 and OVRN bits are set high. Stream-to-FIFO mode is sensitive

to the trigger level and not to the trigger edge; this means that if Stream-to-FIFO is in FIFO

mode and the interrupt condition disappears, the FIFO buffer returns to Stream mode

because the IA bit becomes zero. It is recommended to latch the interrupt signal used as the

FIFO trigger in order to avoid losing interrupt events. If the selected interrupt is latched, it is

necessary to read the OUTS2 register to clear the INT_SM2 bit; after reading, the INT_SM2

bit takes 2*ODR to go low.

In Stream mode the FIFO buffer continues filling, when the buffer is full, the OVRN bit is set

high and the next samples overwrite the oldest. When a trigger occurs, two different cases

can be observed:

If the FIFO buffer is already full (OVRN = “1”), it stops collecting data at the first sample

after trigger. FIFO content is composed of #30 samples collected before the trigger

event, the sample that has generated the interrupt event and one sample after trigger.

If the FIFO is still not full (initial transient), it continues filling until it gets full (OVRN =

“1”) and then, if the trigger is still present, it stops collecting data.

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