AN3027 datasheet(32/41 Pages) STMICROELECTRONICS

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L6563H: high-voltage startup transition-mode PFC

AN3027

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Doc ID 16134 Rev 4

current, minus the device's consumption, charges the bypass capacitor connected from pin

Vcc to ground and makes its voltage rise almost linearly.

Figure 20.

Timing diagram: normal power-up and power-down sequences

As the Vcc voltage reaches the startup threshold (12 V typ.) the low-voltage chip starts

operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is

it is made with an auxiliary winding in the transformer of the cascaded DC-DC converter and

a steering diode) develops a voltage high enough to sustain the operation. The residual

consumption of this circuit is only the one on the 15 M

Ω resistor (10 mW at 400 Vdc),

typically 50-70 times lower, under the same conditions, as compared to a standard startup

circuit made with external resistors. At converter power-down the DC-DC converter loses

regulation as soon as the input voltage is so low that either peak current or maximum duty

cycle limitation is tripped. Vcc then drops and stop IC activity as it falls below the UVLO

threshold (9.5 V typ.). The Vcc_OK signal is de-asserted as the Vcc voltage goes below a

threshold VCCrestart located at about 6 V. The HV generator can now restart. However, if Vin

< VHVstart, HV_EN is de-asserted too and the HV generator is disabled. This prevents the

converter's restart attempts and ensures monotonic output voltage decay at power-down in

systems where brownout protection (see the relevant section) is not used. If the device

detects a fault due to feedback failure, the pin PWM_LATCH is asserted high (see “feedback

failure protection” section for more details) and, in order to maintain this signal to be

provided to the DC-DC converter, the internal VCCrestart is brought up above VccOff (turn-off

threshold).

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