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AN3027 датащи(PDF) 22 Page - STMicroelectronics

номер детали AN3027
подробное описание детали  How to design a transition-mode PFC pre-regulator
PDF  41 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN3027 датащи(HTML) 22 Page - STMicroelectronics

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Designing a TM PFC
AN3027
22/41
Doc ID 16134 Rev 4
The power dissipated in Rs is given by:
Equation 46
According to the result, two parallel resistors of 0.47
Ω and 0.68 Ω with 0.25 W of power
have been selected.
Pin 3 (MULT): The MULT pin is the second multiplier input. It is connected, through a
resistive divider, to the rectified mains to get a sinusoidal voltage reference. The multiplier
can be described by the relationship:
Equation 47
where:
●
VCS (multiplier output) is the reference for the current sense (VCS_OFFSET is its offset)
●
k = 0.45 (typ.) is the multiplier gain
●
VCOMP is the voltage on pin #2 (E/A output)
●
VMULT is the voltage on pin #3.
●
VFF is the second input to the multiplier for the 1/V
2 function. It compensates the control
loop gain dependence on the mains voltage. The voltage at this pin is a DC level equal
to the peak voltage on pin MULT (pin #3).
A complete description is given by the diagrams of
Figure 11 and Figure 12 which show the
typical multiplier characteristics family. The linear operation of the multiplier is guaranteed
2
rms
s
s
ISW
R
P
⋅
=
()
W
37
.
0
A
18
.
1
27
.
0
P
2
s
=
⋅
Ω
=
2
FF
MULT
COMP
m
OFFSET
_
CS
CS
V
V
)
V
5
.
2
V
(
k
V
V
⋅
−
⋅
+
=
Figure 11.
Multiplier characteristics family for
VFF = 1 V
Figure 12.
Multiplier characteristics family for
VFF = 3 V



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