AN3027 datasheet(20/41 Pages) STMICROELECTRONICS

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Designing a TM PFC

AN3027

20/41

Doc ID 16134 Rev 4

overvoltage is generated by a feedback disconnection, for instance, when one of the upper

resistors of the output divider fails open, an additional circuitry detects the voltage drop of

pin INV. If the voltage on pin INV is lower than 1.66 V (Typ.) and at same time the OVP is

active, a feedback failure is assumed. Thus, the gate drive activity is immediately stopped,

the device is shut down, its quiescent consumption is reduced below 180 µA and the

condition is latched as long as the supply voltage of the IC is above the UVLO threshold. To

restart the system it is necessary to recycle the input power, so that the Vcc voltage of the

L6563S goes below 6 V and that one of the PWM controller goes below its UVLO threshold.

Note that this function offers a complete protection against not only feedback loop failures or

erroneous settings, but also against a failure of the protection itself. Either resistor of the

PFC_OK divider failing short or open or a floating PFC_OK pin results in shutting down of

the IC and stopping the pre-regulator. Moreover, the pin PFC_OK doubles its function as a

non-latched IC disable. A voltage below 0.23 V shuts down the IC, reducing its consumption

below 2 mA. To restart the IC simply let the voltage at the pin go above 0.27 V.

Pin 2 (COMP): This pin is the output of the E/A that is fed to one of the two inputs of the

multiplier. A feedback compensation network is placed between this pin and INV (pin #1). It

has to be designed with a narrow bandwidth in order to avoid that the system rejects the

output voltage ripple (100 Hz) that would lead to a high distortion of the input current

waveform.

A simple criterion to define the capacitance value is to set the bandwidth (BW) from 20 to 30

Hz. The compensation network can be just a capacitor, providing a low-frequency pole as

well as a high DC gain. A more complex network, typically a type-II CRC network providing

2 poles and a zero, is more suitable for constant power loads like a downstream converter.

In case a single capacitor is used, it can be dimensioned using the following formulas:

Equation 42

Equation 43

For a more complex compensation network calculation, please refer to [

2], [3].

For this 100 W TM PFC, a CRC network providing two poles and a zero has been

implemented here, using the following values:

The relevant open loop transfer function and its phase function are shown in

Figure 9 and

Figure 10.

(14)

()

Compensati

outL

outH

⋅

() BW

outL

outH

Compensati

⋅

compP =

680

compS =

Ω

compS

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