AN3027 datasheet(16/41 Pages) STMICROELECTRONICS

16 / 41 page

Designing a TM PFC

AN3027

16/41

Doc ID 16134 Rev 4

The dependence on the input voltage is shown in

Figure 5. On the right, Figure 6 represents

the drain voltage waveform: the MOSFET turn-on occurs just on the valley because the

inductor has depleted its energy and therefore can resonate with the drain capacitance.

Details are in the section concerning the ZCD pin description. It is clear that for an input

voltage theoretically lower than half of the output voltage, the resonance ideally should

reach zero, achieving zero-voltage operation, therefore there are no losses relevant to this

edge. For input voltage corresponding to a positive value of the valley, capacitive losses are

generated. However, the MOSFET turn-on always occurs at the minimum voltage of the

resonance and therefore the losses are minimized.

In practice it is possible to estimate the total switching and capacitive losses by solving the

integral of the switching frequency depending on sin(

θ) on the half-line cycle.

The total losses of the input mains voltage are the sum of the three previous loss functions

Equation 26, Equation 28 and Equation 30 respectively multiplied for the MOSFET

parameters:

Equation 33

Figure 7 shows the trend of the total losses from Equation 33 on the line voltage for the

selected MOSFET STF7NM50N. Capacitive losses are dominant at high mains voltage and

the major contribution came from the conduction losses at low and medium mains voltage.

Figure 5.

θ1 and θ2 dependence on input

voltage

Figure 6.

Capacitive losses

)

VAC

(

)

VAC

(

)

VAC

(

)

VAC

(

cap

fall

cond

)

(

loss

′

⋅

′

⋅

′

⋅

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