AN4035 datasheet(25/42 Pages) STMICROELECTRONICS

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AN4035

On-Chip Emulation (OnCE)

Doc ID 022669 Rev 2

25/41

PC and IR portions of the CPUSCR. Care must be taken to insure that the next instruction

fetch after the single step is to a valid memory location.

For SPC56x devices with VLE, the CTL[IRstat8] bit indicates that the instruction in the IR is

a VLE or non-VLE instruction. The CTL[FFRA], CTL[IRStat8], and the CTL bits indicated by

“*” should be set as appropriate before single stepping. All other CTL bits should be set to

zero. Single stepping can be used during normal execution of the instruction flow or to force

execution of a particular instruction by loading the desired instruction into the IR portion of

the CPUSCR. By forcing execution of particular instructions, single stepping can be used for

memory and register access by the tool.

3.9

Exit from debug mode to normal execution

Exiting debug mode and returning to normal execution is achieved by first clearing the

OCR[DMDIS] and OCR[DR] bits if not already clear while leaving the OCR[MCLK] set. The

next step is to write the appropriate information into the CPU scan chain register

(CPUSCR), followed by a write to OCMD to set the OCMD[GO] bit and OCMD[EX] bit with

the OCMD[RS] field indicating either the CPUSCR or No Register Selected. Once debug

mode has been entered, it is required that a scan in and update to the CPUSCR be

performed prior to exiting debug mode. If continuation of the normal instruction stream is

desired, the external tool is responsible for inspection of the CTL register value when debug

mode was entered to determine if the PC is invalid or needs to be offset prior to exiting

debug mode. Also, the internal state bits indicated by “*” in the CTL should be restored to

their original value when debug mode was entered if continuation of the normal instruction

stream is desired. The IRStatus bits of the CTL should be set to zero with the exception of

CTL[IRStat8] on SPC56x devices with VLE. CTL[IRStat8] indicates if the current instruction

in the IR is a VLE or non-VLE instruction. To begin instruction execution from an arbitrary

location, the PC should be set to the desired location for execution to begin minus 0x4. The

IR should be set to a nop (ex: 0x60000000). Then exit debug mode as mentioned above.

The nop executes, then the core begins fetching instructions at the desired location for

execution.

3.10

GPR access

The OnCE module provides the ability to read and write the general purpose registers

(GPR) while in debug mode. Reading a general purpose register is achieved by single

stepping over an ori instruction. As an example, to read the lower 32 bits of GPR r1, an ori

r1,r1,0 instruction is executed, and the result of the instruction is latched into WBBRlow. The

external tool can then read the contents of WBBRlow by scanning out the CPUSCR.

Writing a register is achieved by single stepping over an ori instruction with the CTL[FFRA]

bit set causing the WBBRlow to be used as the source register for the instruction. As an

example, to write the lower 32 bit of GPR r1, an ori r1, X, 0 is executed with the data to be

written in WBBRlow. The X in the instruction is replaced by the WBBRlow register.

3.11

SPR access

The OnCE module provides the ability to read and write the special purpose registers (SPR)

while in debug mode. Reading a special purpose register is achieved by saving the value in

a GPR, single stepping over a mfspr instruction which brings the spr value into both the

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