AN4035 datasheet(17/42 Pages) STMICROELECTRONICS

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AN4035

On-Chip Emulation (OnCE)

Doc ID 022669 Rev 2

17/41

3.3.1

Example of OnCE register write

OnCE registers can be written by selecting the register using the RS[0:6] field and clearing

the R/W bit in the OnCE command register (OCMD). This requires a scan through the IR

path of the TAP controller state machine to write the OCMD and a scan through the DR path

of the TAP controller state machine to write the selected register. As mentioned above, the

external debug mode bit, DBCR0[EDM], must be set to a logical 1 to allow access to most of

the OnCE registers. Therefore, writing the DCBR0 register to set the EDM bit is used as an

example of a writing a OnCE register. Figure 8 shows the register definition of DBCR0.

Figure 8.

DBCR0 register

The example of writing DBCR0 is divided into two parts: writing OCMD to select a write to

DBCR0, and writing the value 0x80000000 to DBCR0. All data are scanned in least

significant bit first.

010 1000 -010 1011

Reserved

010 1100

Debug Counter Register (DBCNT)

010 1101

Debug PCFIFO (PCFIFO) (read-only)

010 1110 -010 1111

Reserved

011 0000

Debug Status Register (DBSR)

011 0001

Debug Control Register 0 (DBCR0)

011 0010

Debug Control Register 1 (DBCR1)

011 0011

Debug Control Register 2 (DBCR2)

011 0100-101 1111

Reserved

111 0000 -111 1001

General Purpose register selects [0:9]

111 1010

Cache Debug Access Control Register (CDACNTL)

111 1011

Cache Debug Access Data Register (CDADATA)

111 1100

Nexus3-Access

111 1101

Reserved

111 1110

Enable_OnCE

111 1111

Bypass

Table 4.

e200z0 OnCE Register Addressing (continued)

RS[0:6]

EDM

IDM

RST

ICMP

BRT

IRPT

TRAP

IAC1

IAC2

IAC3

IAC4

DAC1

DAC2

Reset

RET

000

DEVT1 DEVT2 DCNT1 DCNT2 CRPT CRET

Reset

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