AN4035 datasheet(24/42 Pages) STMICROELECTRONICS

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On-Chip Emulation (OnCE)

AN4035

24/41

Doc ID 022669 Rev 2

VLE, bits IRstat8 and IRstat9 of the CTL do not exist. Below is a description of the IRStat8

bit.

All other CTL bits are discussed as needed.

IR contains a BookE instruction.

IR contains a PowerPC VLE instruction, aligned in the most significant portion of IR if

16-bit.

3.7.3

Program Counter Register (PC)

The PC stores the value of the program counter that was present when debug mode was

entered. The PC value is affected by operations performed during debug mode and must be

restored prior to exiting debug mode. It may be necessary to adjust the PC before exiting

debug mode according the PCOFST field in the CTL. If the external tool desires to redirect

program flow to an arbitrary location, the PC and IR should be initialized corresponding to

the first instruction to be executed. Alternatively, the IR may be set to a nop instruction and

the PC may be set to the location prior to the location at which it is desired to redirect flow.

When debug mode is exited, the nop executes and then instruction fetch and execution

begins at the location which it is desired to redirect flow.

3.7.4

Write-Back Bus Register (WBBRlow, WBBRhigh)

WBBR is used as a means of passing operand information to/from the CPU from/to the

external tool. Whenever the external tool needs to read the contents of a CPU register or

memory location, it can force the CPU to single step an instruction that brings that

information to WBBR. To write the contents of a CPU register or memory location, the

external tool can force the CPU to single step an instruction that uses the information in

WBBR. For the purpose of this document, only WBBRlow is used. WBBRhigh is used for SPE

instructions that generate 64-bit results or use 64-bit operands. Such instructions are

outside the scope of this document.

3.7.5

Machine State Register (MSR)

The MSR is used to read/write the machine state register of the CPU. This register is

affected by operations performed while in debug mode. If consistency of the machine state

is desired, the MSR should be saved when entering debug mode and restored prior to

exiting debug mode.

3.8

Single step

Single stepping of instructions is achieved by first placing the CPU in debug mode if the

CPU is not already in debug mode. The next step is to write the appropriate information into

the CPU scan chain register (CPUSCR), followed by writing to OCMD to set the OCMD[GO]

bit and clear the OCMD[EX] bit with the OCMD[RS] field indicating either the CPUSCR or

No Register Selected. Once debug mode has been entered, it is required that a scan in and

update to the CPUSCR must be performed prior to single stepping. For single step, the CPU

returns to debug mode after executing a single instruction. The external tool should read the

OnCE status register (OSR) to verify that the CPU has returned to debug mode without the

OSR. During single step, exception conditions can occur, if not masked, and may prevent

the desired instruction from being executed. After stepping over the instruction, the core

fetches the next instruction. The new program counter and instruction are loaded into the

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