AN4035 datasheet(20/42 Pages) STMICROELECTRONICS

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On-Chip Emulation (OnCE)

AN4035

20/41

Doc ID 022669 Rev 2

Figure 13.

OnCE status register

Figure 14 shows reading the OnCE status register on TDO while writing the OCMD on TDI

assuming the TAP controller state machine is initially in the RUN-TEST/IDLE state. The

state machine is returned to the RUN-TEST/IDLE state when the read is complete. The

OCMD is written with the value 0b10_0001_0001 choosing a read of No Register Selected.

The data read on TDO from the OnCE status register is 0b10_0000_1001 showing that the

OSR[MCLK] and OSR[DEBUG] status bits are set. All data is scanned in and out least

significant bit first.

Figure 14.

Signal transitions of reading the OnCE status register

3.5

Entering debug mode during reset

There are several different methods of entering debug mode. This section covers entering

debug mode while the RESET pin is asserted. Entering debug mode while the RESET pin is

asserted is useful, because the debug session begins with the CPU in a known state. The

OnCE control register (OCR) controls entry into debug mode for this method. Figure 15

shows the register definition for the OCR.

Figure 15.

OnCE control register

The OCR[DR] bit is the CPU debug request control bit and requests the CPU to

unconditionally enter debug mode. The OCR[WKUP] bit is the wakeup request bit used to

guarantee that the CPU clock is running. Debug status and CPU clock activity can be

determined by reading the DEBUG and MCLK bits in the OnCE status register. After

MCLK

ERR

CHKSTOP

RESET

HALT

STOP

DEBUG

0123456789

0DMDIS

DW DI

DM DG DE

FDB DR

9 10 11 12 13 14 15

17 18

25 26 27

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