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AN4035 датащи(PDF) 14 Page - STMicroelectronics |
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AN4035 датащи(HTML) 14 Page - STMicroelectronics |
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14 / 42 page ![]() On-Chip Emulation (OnCE) AN4035 14/41 Doc ID 022669 Rev 2 TEST/IDLE state. The state machine is returned to the RUN-TEST/IDLE state when the write is complete. Figure 6. Signal transitions for enabling the OnCE TAP controller 3.2 OnCE register access The OnCE module provides several registers for static debug support. The OnCE command register (OCMD) is a special register and acts as the IR for the TAP controller state machine and is used to access other OnCE resources. 3.3 OnCE command register The OnCE command register (OCMD) is a 10-bit shift register that receives its serial data from the TDI pin and acts as the IR register of the TAP controller state machine. The OCMD is updated when the TAP controller enters the UPDATE-IR state. It contains fields for Figure 5. Steps for enabling the OnCE TAP controller TCK tick TMS TDI Resulting state 1 1 X SELECT-DR-SCAN 2 1 X SELECT-IR-SCAN 3 0 X CAPTURE-IR 40 X SHIFT-IR 50 1 SHIFT-IR 60 0 SHIFT-IR 70 0 SHIFT-IR 80 0 SHIFT-IR 91 1 SHIFT-IR 10 1 X UPDATE-IR 11 0 X RUN-TEST/IDLE |
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