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AN4035 датащи(PDF) 16 Page - STMicroelectronics |
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AN4035 датащи(HTML) 16 Page - STMicroelectronics |
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16 / 42 page ![]() On-Chip Emulation (OnCE) AN4035 16/41 Doc ID 022669 Rev 2 Table 4 shows the OnCE register addresses. Access to the registers CPUSCR, DAC1-2, DBCNT, DBCR0-3, DBSR, and IAC1-4 require that the external debug mode bit, DBCR0[EDM], be set to a logical 1. Only the DBCR0[EDM] is accessible in the DBCR0 register prior to that bit being set. Setting DBCR0[EDM] enables external debug mode and disables software updates to debug registers. The CPU should be placed in debug mode via the OCR[DR] bit prior to setting the DBCR0[EDM] bit. 2EX 0 Remain in debug mode 1 Leave debug mode If the EX bit is set, the processor leaves debug mode and resume normal operation until another debug request is generated. The Exit command is executed only if the Go command is issued, and the operation is a read/write to CPUSCR or a read/write to “No Register Selected”. Otherwise the EX bit is ignored. The processor leaves debug mode after the TAP controller Update-DR state is entered. Note that if the DR bit in the OnCE control register is set or remains set, or if a bit in the DBSR is set, or if a bit in the DBSR is set and DBCR0[EDM]=1 (external debug mode is enabled), then the processor may return to debug mode without execution of an instruction, even though the EX bit was set. 3-9 RS Register Select The Register Select bits define which register is source (destination) for the read (write) operation. Attempted writes to read-only registers are ignored. Table 3. OnCE command register bit definitions (continued) Bit(s) Name Description Table 4. e200z0 OnCE Register Addressing RS[0:6] Register selected 000 0000 Reserved 000 0001 Reserved 000 0010 JTAG ID (read-only) 000 0011-000 1111 Reserved 001 0000 CPU Scan Register (CPUSCR) 001 0001 No Register Selected (Bypass) 001 0010 OnCE Control Register (OCR) 001 0011-001 1111 Reserved 010 0000 Instruction Address Compare 1 (IAC1) 010 0001 Instruction Address Compare 2 (IAC2) 010 0010 Instruction Address Compare 3 (IAC3) 010 0011 Instruction Address Compare 4 (IAC4) 010 0100 Data Address Compare 1 (DAC1) 010 0101 Data Address Compare 2 (DAC2) 010 0110 Data Value Compare 1 (DVC1) 010 0111 Data Value Compare 2 (DVC2) |
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