AN3077 datasheet(67/82 Pages) STMICROELECTRONICS

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AN3077

ECC logic test

6.1

Overview

This appendix describes the required information on how to develop the software for such

ECC logic test.

A flash memory ECC logic test is needed to perform a test to check flash memory ECC logic

every FTTI (10 ms).

The goal is to ensure high coverage of the faults in ECC logic with minimum performance

penalty to customer’s application. Thus, the performance penalty must be less than 2%

which means that the test lasts less than 200 µs considering a FTTI of 10 ms.

The Device_Number flash memory has a UTEST (user-test) mode ECC logic check feature

which can be utilized for this ECC logic test. A data pattern with walking 0 through data and

ECC parity bits can be applied during the ECC logic check procedure to achieve high fault

coverage of the ECC logic and fast execution.

6.2

Data pattern - Walking 0

To reach the needed performances the use of the data pattern with walking 0 through data

and ECC parity bits must be used. Table 20 shows the data vectors.

Table 20. Data pattern used by the ECC logic test(1)

Each vector is a 72-bit ECC code-word.

Data vector number

8-bit ECC parity bits

64-bit data bits

0xFF

0xFFFF_FFFF_FFFF_FFFE

0xFF

0xFFFF_FFFF_FFFF_FFFD

0xFF

0xFFFF_FFFF_FFFF_FFFB

0xFF

0xFFFF_FFFF_FFFF_FFF7

0xFF

0xFFFF_FFFF_FFFF_FFEF

0xFF

0xFFFF_FFFF_FFFF_FFDF

0xFF

0xFFFF_FFFF_FFFF_FFBF

0xFF

0xFFFF_FFFF_FFFF_FF7F

...

0xFF

0xBFFF_FFFF_FFFF_FFFF

0xFF

0x7FFF_FFFF_FFFF_FFFF

0xFE

0xFFFF_FFFF_FFFF_FFFF

0xFD

0xFFFF_FFFF_FFFF_FFFF

...

0x7F

0xFFFF_FFFF_FFFF_FFFF

0xFF

0xFFFF_FFFF_FFFF_FFFF

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