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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LXT970A датащи(PDF) 63 Page - Intel Corporation |
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LXT970A датащи(HTML) 63 Page - Intel Corporation |
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63 / 74 page  Dual-Speed Fast Ethernet Transceiver — LXT970A Datasheet 63 5.0 Register Definitions The LXT970A register set includes a total of twelve 16-bit registers. Refer to Table 44 for a complete register listing. • Seven base registers (0 through 6) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signalling for 10/100 Mbps Auto-Negotiation” sections of the IEEE 802.3 specification (Register 7, Next Page, is not supported). • Five additional registers (16 through 20) are defined in accordance with the IEEE 802.3 specification for adding unique chip functions. Table 44. Register Set Address Register Name Bit Assignments 0 Control Register Refer to Table 45 on page 64 1 Status Register Refer to Table 46 on page 65 2 PHY Identification Register 1 Refer to Table 47 on page 66 3 PHY Identification Register 2 Refer to Table 48 on page 66 4 Auto-Negotiation Advertisement Register Refer to Table 49 on page 67 5 Auto-Negotiation Link Partner Ability Register Refer to Table 50 on page 68 6 Auto-Negotiation Expansion Register Refer to Table 51 on page 69 16 Mirror Register Refer to Table 52 on page 69 17 Interrupt Enable Register Refer to Table 53 on page 70 18 Interrupt Status Register Refer to Table 54 on page 70 19 Configuration Register Refer to Table 55 on page 71 20 Chip Status Register Refer to Table 56 on page 72 |
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