LXT970A datasheet(4/74 Pages) INTEL

4 / 74 page

LXT970A — Dual-Speed Fast Ethernet Transceiver

Datasheet

2.8.2.3 Carrier Sense (CRS) ................................................................. 38

2.8.3

Twisted-Pair PMD Layer ........................................................................ 39

2.8.3.1 Scrambler/Descrambler (100TX Only) ...................................... 39

2.8.3.2 Baseline Wander Correction

(100TX Only)39

2.8.3.3 Polarity Correction..................................................................... 39

2.8.4

Fiber PMD Layer .................................................................................... 39

2.8.5

Additional Operating Features ............................................................... 40

2.8.6

Low-Voltage-Fault Detect....................................................................... 40

2.8.7

Power Down Mode ................................................................................. 40

2.8.8

Software Reset....................................................................................... 40

2.8.9

Hardware Reset ..................................................................................... 40

3.0

Application Information......................................................................................... 41

3.1

Magnetics Information ......................................................................................... 41

3.2

Crystal Information .............................................................................................. 41

3.3

Design Recommendations .................................................................................. 42

3.3.1

General Design Guidelines .................................................................... 42

3.3.2

Power Supply Filtering ........................................................................... 42

3.3.3

Ground Noise ......................................................................................... 43

3.3.4

Power and Ground Plane Layout Considerations .................................. 43

3.3.5

Interfaces for Twisted-Pair /Fiber ........................................................... 43

3.3.5.1 Twisted-Pair .............................................................................. 43

3.3.5.2 Fiber .......................................................................................... 44

3.3.6

Interface for the MII ................................................................................ 44

3.3.6.1 Transmit Hold Time Adjustment ................................................ 44

3.3.6.2 MII Terminations........................................................................ 44

3.3.7

Typical Application ................................................................................. 45

3.3.7.1 Voltage Divider For MF Inputs................................................... 45

4.0

Test Specifications.................................................................................................. 47

5.0

6.0

Mechanical Specifications ................................................................................... 73

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