LXT970A datasheet(25/74 Pages) INTEL

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Dual-Speed Fast Ethernet Transceiver — LXT970A

Datasheet

and an optional interrupt line (MDINT). The LXT970A can signal an interrupt using the MDIO

signal as shown in Figure 8. The user can also assign a separate pin for this function. If bit 17.1 = 1,

pin 2 (FDS/MDINT) will be used as an MDINT pin.

The protocol allows one controller to communicate with multiple LXT970A devices. The MF pins

control one bit each of the 5-bit address setting. Each LXT970A is assigned an MII address

between 0 and 31. Details of the MF inputs are shown in Table 7 on page 14. Timing for the MDIO

Interface is shown in Table 42 on page 61. Read and write operations are shown in Figure 9 and

Figure 10. Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High,

the MDIO operates as a read-only interface. When MDDIS is Low, read and write are enabled.

The LXT970A supports twelve 16-bit MDIO registers. Registers 0-6 are required and their

functions are specified by the IEEE 802.3 specification. Additional registers are included for

expanded functionality. The MDIO Register set for the LXT970A is described in Table 45 through

Table 56. Specific bits in the registers are referenced using an “X.Y” notation, where X is the

MII Management Interrupt

The MDINT/FDS pin functions as a management data interrupt on the MII when 17.1 = 1. An

active Low on this pin indicates a status change on the LXT970A. The interrupt is activated when

changes are made to the following conditions:

• Link Status

• Duplex Status

This interrupt is cleared by sequentially reading Register 1 and Register 18.

Figure 8. MDIO Interrupt Signaling

Figure 9. Management Interface - Read Frame Structure

Figure 10. Management Interface - Write Frame Structure

MDC

MDIO

Interrupt

Turn

Around

Idle

INT

Read Data

Sourced by

LXT970A

MDIO FRAME

MDC

MDIO

(Read)

32 "1"s

011

Preamble

SFD

Op Code

PHY Address

Turn

Around

D15

D14

Data

Idle

Write

Read

D15

D14

Idle

MDC

MDIO

(Write)

32 "1"s

0101

Preamble

SFD

Op Code

PHY Address

Turn

Around

D15

D14

Data

Idle

Write

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