LXT970A datasheet(5/74 Pages) INTEL

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Datasheet

Dual-Speed Fast Ethernet Transceiver — LXT970A

Figures

LXT970A Block Diagram ....................................................................................... 9

LXT970A Pin Assignments ................................................................................. 10

Network Interface Card (NIC) Application .......................................................... 18

MII Interface ....................................................................................................... 20

MII Data Interface ...............................................................................................21

Loopback Paths .................................................................................................. 23

Repeater Block Diagram .................................................................................... 24

MDIO Interrupt Signaling .................................................................................... 25

Management Interface - Read Frame Structure ................................................. 25

Management Interface - Write Frame Structure ................................................. 25

LXT970A Initialization Sequence ....................................................................... 30

Auto-Negotiation Operation ................................................................................ 31

100BASE-TX Frame Structure ........................................................................... 33

100BASE-TX Data Flow ..................................................................................... 33

LXT970A Protocol Sublayers ............................................................................. 36

100BASE-TX Reception with No Errors ............................................................. 37

100BASE-TX Reception with Invalid Symbol .................................................... 37

100BASE-TX Transmission with No Errors ....................................................... 37

100BASE-TX Transmission with Collision ......................................................... 37

Voltage Divider ................................................................................................... 45

Typical Interface Circuitry ................................................................................... 46

MII - 100BASE-TX Receive Timing / 4B Mode ................................................... 51

MII - 100BASE-TX Transmit Timing / 4B Mode ................................................. 52

MII - 100BASE-TX Receive Timing / 5B Mode ................................................... 53

100BASE-TX Transmit Timing / 5B Mode .......................................................... 54

MII - 100BASE-FX Receive Timing / 4B Mode ................................................... 55

MII - 100BASE-FX Transmit Timing / 4B Mode ..................................................56

MII - 10BASE-T Receiving Timing ...................................................................... 57

MII - 10BASE-T Transmit Timing ....................................................................... 58

10BASE-T SQE (Heartbeat) Timing ................................................................... 59

10BASE-T Jab and Unjab Timing ...................................................................... 59

Auto Negotiation and Fast Link Pulse Timing .................................................... 60

Fast Link Pulse Timing ....................................................................................... 60

MDIO Timing when Sourced by STA ................................................................. 61

MDIO Timing when Sourced by PHY ................................................................. 61

Power-Down Recovery Timing (Over Recommended Range) ........................... 62

PHY Identifier Bit Mapping ................................................................................. 66

64-Pin QFP Package Diagram ........................................................................... 73

64-Pin TQFP Package Diagram ......................................................................... 74

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