| поискавой системы для электроныых деталей |
|
IO20PDB0V0 датащи(PDF) 127 Page - Microsemi Corporation |
|
|
|||||||||||||||||||||||||||||
IO20PDB0V0 датащи(HTML) 127 Page - Microsemi Corporation |
|
127 / 197 page ![]() SmartFusion Customizable System-on-Chip (cSoC) Re vi s i on 12 5 - 13 SPI_1_DO Out 1 Data output. Second SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6). SPI_1_SS Out 1 Slave select (chip select). Second SPI. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6). Universal Asynchronous Receiver/Transmitter (UART) Peripherals UART_0_RXD In 1 Receive data. First UART. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6). UART_0_TXD Out 1 Transmit data. First UART. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6). UART_1_RXD In 1 Receive data. Second UART. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6). UART_1_TXD Out 1 Transmit data. Second UART. Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6). Ethernet MAC MAC_CLK In Rise Receive clock. 50 MHz ± 50 ppm clock source received from RMII PHY. Can be left floating when unused. MAC_CRSDV In High Carrier sense/receive data valid for RMII PHY Can also be used as an FPGA User IO (see "IO" on page 5-6). MAC_MDC Out Rise RMII management clock Can also be used as an FPGA User IO (see "IO" on page 5-6). MAC_MDIO In/Out 1 RMII management data input/output Can also be used as an FPGA User IO (see "IO" on page 5-6). MAC_RXDx In 2 Ethernet MAC receive data. Data recovered and decoded by PHY. The RXD[0] signal is the least significant bit. Can also be used as an FPGA User I/O (see "IO" on page 5-6). MAC_RXER In HIGH Ethernet MAC receive error. If MACRX_ER is asserted during reception, the frame is received and status of the frame is updated with MACRX_ER. Can also be used as an FPGA user I/O (see "IO" on page 5-6). MAC_TXDx Out 2 Ethernet MAC transmit data. The TXD[0] signal is the least significant bit. Can also be used as an FPGA user I/O (see "IO" on page 5-6). MAC_TXEN Out HIGH Ethernet MAC transmit enable. When asserted, indicates valid data for the PHY on the TXD port. Can also be used as an FPGA User I/O (see "IO" on page 5-6). Name Type Polarity/ Bus Size Description |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |