IO20PDB0V0 datasheet(124/197 Pages) MICROSEMI

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Pin Descriptions

5- 10

R e v i sio n 1 2

JTAG Pins

SmartFusion cSoCs have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate,

even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the

SmartFusion cSoC part must be supplied to allow JTAG signals to transition the SmartFusion cSoC.

Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and

simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used,

the VJTAG pin together with the TRSTB pin could be tied to GND.

Name

Type

Polarity/

Bus Size

Description

JTAGSEL

JTAG controller selection

Depending on the state of the JTAGSEL pin, an external JTAG controller will either

see the FPGA fabric TAP/auxiliary TAP (High) or the Cortex-M3 JTAG debug

interface (Low).

The JTAGSEL pin should be connected to an external pull-up resistor such that the

default configuration selects the FPGA fabric TAP.

TCK

Test clock

Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an

internal pull-up/-down resistor. If JTAG is not used, it is recommended to tie off TCK

to GND or VJTAG through a resistor placed close to the FPGA pin. This prevents

JTAG operation in case TMS enters an undesired state.

Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements.

Refer to Table 5-1 on page 5-11 for more information.

Can be left floating when unused.

TDI

Test data

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal

weak pull-up resistor on the TDI pin.

TDO

Out

Test data

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

TMS

HIGH

Test mode select

The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO,

TRST). There is an internal weak pull-up resistor on the TMS pin.

Can be left floating when unused.

TRSTB

HIGH

Boundary scan reset pin

The TRST pin functions as an active low input to asynchronously initialize (or reset)

the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST

pin. If JTAG is not used, an external pull-down resistor could be included to ensure

the TAP is held in reset mode. The resistor values must be chosen from Table 5-1 on

page 5-11 and must satisfy the parallel resistance value requirement. The values in

Table 5-1 on page 5-11 correspond to the resistor recommended when a single

device is used. The values correspond to the equivalent parallel resistor when

multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entering an undesired

JTAG state. In such cases, it is recommended that you tie off TRST to GND through a

resistor placed close to the FPGA pin.

The TRSTB pin also resets the serial wire JTAG – debug port (SWJ-DP) circuitry

within the Cortex-M3.

Can be left floating when unused.

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