L6717 datasheet(26/56 Pages) STMICROELECTRONICS

26 / 56 page

Power manager I2C

L6717

26/56

Doc ID 17326 Rev 1

Power manager I2C

L6717 features a secondary power manager I2C bus to easy the implementation of power

management features as well as over-speeding for “enthusiastic” users. The power

manager I2C bus is operative after the PWRGOOD signal is driven high at the end of the

soft-start.

Power manager I2C is a two wire, SCL (Clock) and SDA (Data), bus connecting a single

master to one or more slaves (L6717) separately addressable. The master initiates and

terminates I2C transactions and drives both the clock, SCL, and the data, SDA, during a

transaction. The slave receives the I2C transactions and acts accordingly.

Power manager I2C wire protocol is based on fast-mode I2C.

Power manager I2C address configuration can be programmed through ADDR pin while

I2CDIS pin allows to disable the bus. See Table 10.

Power manager I2C and SVI bus are two independent buses working in parallel. In case two

commends are issued in the same time on the two buses, L6717 performs them in the same

time.

Table 10.

Power manager I2C configuration

6.1

Power manager commands

Power manager I2C master issues different command sequences to modify several voltage

positioning parameters for CORE and/or NB Sections of L6717.

Moreover the power manager I2C commands allow to configure DPM and other power-

saving-related features.

During a power manager command:

– The bus master sends the start (START) sequence followed by the address of the

controller which the power manager command applies. The bus master then sends

the write (WRITE) bit. After the write bit, the voltage regulator (VR, L6717) sends the

acknowledge (ACK) bit.

– The bus master sends the command code during the command phase. The VR

(L6717) sends the acknowledge (ACK) bit after the command phase.

– The bus master sends the data stream related to the command phase previously

issued (if applicable). The VR (L6717) sends the acknowledge (ACK) bit after the data

stream. Finally, the bus master sends the stop (STOP) sequence.

– After the VR (L6717) has detected the STOP sequence, it performs operations

according to the command issued by the bus master.

I2CDIS

ADDR

Description

3.3V

n/a

Power manager

I2C disabled.

SDA/OVP now becomes OVP to program the OV threshold for

both CORE and NB sections.

SCL/OS now becomes OS to program Offset for the CORE

section.

OPEN

3.3V

It sets

I2C address to 1100111.

OPEN

It sets

I2C address to 1100110 (default).

L6717 датащи(PDF) 26 Page - STMicroelectronics

L6717 датащи(HTML) 26 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

датащи скачать

ссылки URL