L6717 datasheet(24/56 Pages) STMICROELECTRONICS

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Hybrid CPU support and CPU_TYPE detection

L6717

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Doc ID 17326 Rev 1

5.4.2

PWROK de-assertion

Anytime PWROK de-asserts, while EN is asserted, the controller uses the previously stored

Pre-PWROK Metal VID and sets both CORE and NB planes voltage to the corresponding

level performing an on-the-fly VID transition.

Anytime the PWROK is de-asserted the PWRGOOD is tied low; after being pulled low the

PWRGOOD is treated appropriately and kept de-asserted until the output voltage of both

CORE and NB sections is within the PWRGOOD validity window referred to Pre-PWROK

Metal VID.

5.4.3

PSI_L and efficiency optimization at light-load

PSI_L is an active-low flag (i.e. low logic level when asserted) that can be set by the CPU to

allow the VR to enter power-saving mode to maximize the system efficiency when in light-

load conditions. The status of the flag is communicated to the controller through the SVI

bus.

When the PSI_L flag is asserted by the CPU through the SVI bus, the device adjusts the

phase number according to the programmed strategy. Default PSI_L strategy consists in

working in single phase. PSI_L strategy can be disabled as well as re-configured through

specific Power Manager I2C commands. See Section 6 for details.

When CPU issues PSI_L flag, L6717 adjusts phase number according to the selected

PSI_L strategy: the device sets HiZ on the related phases and re-configures internal phase-

shift to maintain the correct interleaving among active phases. Furthermore, the internal

current-sharing is adjusted considering the phase number reduction.

When PSI_L is de-asserted, the device will return to the original configuration.

Start-up is performed with all the configured phases enabled.

When PSI_L is active L6717 performs on-the-fly VID transitions with all the programmed

phases.

NB section is not impacted by PSI_L status change.

Figure 7 shows an example of the efficiency improvement that can be achieved by enabling

the PSI management.

Figure 7.

System efficiency enhancement by PSI

1 PHASE

4 PHASE

1 PHASE

4 PHASE

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