L6717 datasheet(11/56 Pages) STMICROELECTRONICS

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L6717

Pins description and connection diagrams

Doc ID 17326 Rev 1

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SDA / OVP

SDA - power manager

I2C data.

When power manager

I2C is enabled, this is the data connection.

See Section 6 for details.

OVP - over voltage setting.

When power manager

I2C is disabled (VID4 / I2CDIS to 3.3V) the pin is used to set

the OVP protection for CORE and NB sections. Define the OVP threshold by

connecting the pin to the center tap of a voltage divider from 3V3 to SGND.

See Section 8.1 for details.

SCL / OS

SCL - power manager

I2C clock.

When power manager

I2C is enabled, this is the clock connection.

See Section 6 for details.

OS - CORE section offset.

When power manager

I2C is disabled (VID4 / I2CDIS to 3.3V) this pin is internally set

to 1.24V(2.0V): connecting a ROS resistor to GND (3.3V) allows setting a current that

is mirrored into FB pin in order to program a positive (negative) offset according to the

selected RFB. Short to GND to disable the function. See Section 7.4 for details.

27, 28

PWM4,

PWM3

PWM output for external drivers.

Connect to external drivers PWM inputs. The device is able to manage HiZ status by

setting the pins floating.

By shorting to GND PWM4 or PWM3 and PWM4, it is possible to program the CORE

section to work at 3 or 2 phase respectively.

See Section 5.4.4 for details about HiZ management.

VID5 /

ADDR

Voltage identification pin -

I2C address pin.

Internally pulled-low by 10

μA, it programs the output voltage in PVI mode. In SVI

mode, the pin is monitored on the EN pin rising-edge to modify the

I2C address. See

Section 5 for details.

VID4 /

I2CDIS

Voltage identification pin -

I2C disable pin.

Internally pulled-low by 10

μA, it programs the output voltage in PVI mode. In SVI

mode, the pin is monitored on the EN pin rising-edge to enable/disable the

I2C. See

Section 5 for details.

VID3 / SVC

Voltage IDentification Pin - SVI clock pin.

Internally pulled-low by 10

μA, it programs the output voltage in both SVI and PVI

modes. In SVI mode, the 10

μA pull down is disabled. See Section 5 for details.

VID2 / SVD

Voltage identification pins - SVI data pin.

Internally pulled-low by 10

μA, it programs the output voltage in both SVI and PVI

modes. In SVI mode, the 10

μA pull down is disabled. See Section 5 for details.

VID1 /

CORETYPE

Voltage identification pin.

Internally pulled-low by 10

μA, it programs the output voltage in PVI mode. The pin is

monitored on the EN pin rising-edge to define the operative mode of the controller

(SVI or PVI). See Section 5 for details.

VID0 / VFIX

Voltage identification pin.

Internally pulled-low by 10

μA, it programs the output voltage in PVI mode. If the pin is

pulled to 3.3V, the device enters V_FIX mode and SVI commands are ignored.

See Section 5 for details.

Table 2.

Pin description (continued)

Pin#

Name

Function

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