DAC5687IPZP datasheet(72/79 Pages) TI

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DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

Changes from Revision D (July 2006) to Revision E ...................................................................................................... Page

• Inverted CLK2 waveform in Figure 50 timing diagram ....................................................................................................... 44

• Deleted Δ < t

align from Figure 51 timing diagram.................................................................................................................. 44

Changes from Revision C (April 2006) to Revision D .................................................................................................... Page

• For pins 34 and 92 in pinout diagram, changed "MSB" to "MSB or LSB," and for pins 55 and 71 changed "LSB" to

"LSB or MSB," to reflect option of bus reversal. .................................................................................................................... 3

• Added V

IH and VIL specifications for IOVDD = 1.8 V ............................................................................................................. 9

• In register CONFIG3, added sentence to counter_mode(2:0) description indicating that counter mode replaces

digital signal with a counter signal ....................................................................................................................................... 27

• In register NCO_FREQ_2, changed address to 0x0B......................................................................................................... 28

• In register NCO_FREQ_3, changed address to 0x0C......................................................................................................... 28

• In register DACA_DACB_GAIN_1, added daca_gain(11:8) to description ......................................................................... 30

• In the description of instruction bytes N1 and N0, added description of multibyte transfers............................................... 32

• For FIR filters, corrected description (color and type) of lines in Figure 38......................................................................... 34

• Changed "... FMIX + f

DAC/2" to "FMIX + CMIX with fDAC/2" ................................................................................................. 36

• Changed f

DAC to fNCO in Figure 39........................................................................................................................................ 36

• To DAC Offset Control section, appended description of the transition between offset values during four DAC clock

cycles (two paragraphs and Table 11)................................................................................................................................. 39

• Added sentence in external clock mode description explaining that the PLLLOCK output should not be used above

100 MHz for IOVDD = 1.8 V ................................................................................................................................................ 41

• In dual clock mode equation, changed "f

align" to "talign"......................................................................................................... 43

• Appended paragraph to Interleave Bus Mode section describing issues with synchronization in PLL mode with

interleaved data ................................................................................................................................................................... 45

• First sentence of Input FIFO section, changed "DAC clock mode" to "external clock mode" ............................................. 45

• Changed second "=" in equation to a "–"............................................................................................................................. 52

• Changed "The external output resistors are referred to an external ground." to "The external output resistors are

referred to AVDD." .............................................................................................................................................................. 52

• Changed "Exceeding the output compliance voltage..." to "Exceeding the minimum output compliance voltage...".......... 52

• Changed "does not exceed 0.5 V" to "is in the range of AVDD ±0.5 V."............................................................................. 52

• Appended sentence, "The pullup and pulldown circuitry is approximately equivalent to 100 kΩ." ..................................... 55

• Changed caption of Figure 65 ............................................................................................................................................. 56

• Changed "...it is suggested that ω

d be set... to "...it is suggested that φd be set..." ............................................................. 57

• In last sentence of paragraph, changed "1.56-V

PP differential" to "1.52-VPP differential" ................................................... 58

• Changed example of an interface to a 1.5-V common-mode device to an interface to a 3.3-V common mode for

TRF3703-33 ......................................................................................................................................................................... 59

• In Table 16, changed value in top row of Frequency/f

DAC column from 0.7 to 0.07 ........................................................... 64

• In text for example #2, changed "...f

DAC/2 and fDAC/4 signal is adjusted..." to "...fDAC/2 spurious signal is adjusted..." ...... 65

• Changed referenced figure number to Figure 82 ................................................................................................................ 70

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