DAC5687IPZP datasheet(45/79 Pages) TI

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Input FIFO

B0166-01

D Q

Input

Pointer

Generation

PLLLOCK

MUX

CLK1

CLK1C

{PLLVDD,inv_plllock,dual_clk}

MUX

Clock

Generator

Resynchonized

DA[15:0],DB[15:0]

andPHSTR

syncsource

{TXENABLE,PHSTR,QFLAG,DB[15],

DA[15]oneshot,SIFwrite,alwaysoff}

CLK2

CLK2C

PLL VCO

fifo_bypass

in_sel_d

in_sel_c

in_sel_b

in_sel_a

q_b

q_c

q_d

q_in

q_out

clk_in

clk_out

sel_q_a

sel_q_d

sel_q_c

sel_q_b

sync

D Q

DA[15:0],

DB[15:0],

PHSTR

D Q

q_a

Output

Pointer

Generation

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

When using interleaved input mode with the PLL enabled, input clock CLK1 is at 2

× the frequency of the input to

FIR1. If the dividers for multiple DAC5687s are not synchronized, there can be a one-CLK1-period output time

difference between devices that have synchronized input data. However, the divider that generates the clock for

the FIR1 input is not connected to the DAC5687 synchronization circuitry. In general, dual-clock mode is

recommended in applications where multiple DAC5687s must be synchronized in interleaved input mode. If PLL

mode is required, the following workaround using the asynchronous RESET pin synchronizes the clock dividers.

With the CLK1 input off and the chip powered, set RESET low for >50 ns and then high for all devices,

simultaneously restarting CLK1. Note that the devices must be reprogrammed after the reset sequence. If CLK1

is kept active during the reset sequence, then multiple devices are typically reset to the same clock phase, but

because the RESET pin is asynchronous, the clock divider on two devices can come out of reset at slightly

different times.

In external clock mode, where the DAC5687 is clocked at the DAC update rate, the DAC5687 has an optional

input FIFO that allows latching of DA[15:0], DB[15:0] and PHSTR based on a user-provided CLK1/CLK1C input

or the input data rate clock provided to the PLLLOCK pin. The FIFO can be bypassed by setting register

fifo_bypass in CONFIG0 to 1.

The input interface FIFO incorporates a four-sample register file, an input pointer, and an output pointer.

Initialization of the FIFO pointers can be programmed to one of seven different sources.

Figure 52. DAC5687 Input FIFO Logic

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