DAC5687IPZP datasheet(47/79 Pages) TI

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Even/Odd Input Mode

Synchronization

NCO Synchronization

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

Once initialized, the FIFO input pointer advances using clk_in and the output pointer advances using clk_out,

providing an elastic buffering effect. The phase relationship between clk_in and clk_out can wander or drift until

the output pointer overruns the input pointer or vice versa.

The DAC5687 has a double data rate input mode that allows both input ports to be used to multiplex data onto

one DAC channel (A). In the even/odd mode, the FIR3 filter can be used to interpolate the data by 2

×. The

even/odd input mode is enabled by setting half_rate in CONFIG3. The maximum input rate for each port is 250

MSPS, for a combined rate of 500 MSPS.

The DAC5687 has several digital circuits that can be synchronized to a known state. The circuits that can be

synchronized are the fine mixer (NCO), coarse mixer (fixed fS/2 or fS/4 mixer), the FIFO input and output

pointers, and the internal clock divider.

Table 13. Synchronization in Different Clock Modes

Serial Interface Register Bits

DA, DB,

Clock

PLLVDD

PHSTR, and

Description

Mode

TXENABLE

fifo_bypass

dual_clk

inv_plllock

Latch

Single

0 V

PLLLOCK

Signal at the PLLLOCK output pin is used to clock the

external

rising edge

PHSTR signal into the chip. The PLLLOCK output

clock

clock is generated by dividing the CLK2/CLK2C input

PLLLOCK

without

signal by the programmed interpolation and interface

falling edge

FIFO

settings.

Single

0 V

PLLLOCK

Signal at the PLLLOCK output pin is used to clock the

external

rising edge

PHSTR signal into the chip. The PLLLOCK output

clock with

clock is generated by dividing the CLK2/CLK2C input

PLLLOCK

FIFO

signal by the programmed interpolation and interface

falling edge

settings. Enabling the FIFO allows the chip to function

with large loads on the PLLLOCK output pin at high

input rates. The FIFO must be initialized first in this

mode.

Dual

0 V

CLK1/CLK1C

The CLK1/CLK1C input signal is used to clock in the

external

PHSTR signal. CLK1/CLK1C and CLK2/CLK2C are

clock

both input to the chip, and the phase relationship

without

must be tightly controlled.

FIFO

Dual

0 V

CLK1/CLK1C

The CLK1/CLK1C input signal is used to clock in the

external

PHSTR signal. CLK1/CLK1C and CLK2/CLK2C are

clock with

both input to the chip, but no phase relationship is

FIFO

required. The FIFO input circuits are used to manage

the clock domain transfers. The FIFO must be

initialized in this mode.

PLL

3.3 V

CLK1/CLK1C

The CLK1/CLK1C input signal is used to clock in the

enabled

PHSTR signal. The FIFO must be bypassed when the

PLL is enabled.

The phase accumulator in the NCO block (see the Fine Mixer (FMIX) section and Figure 39 for a description of

the NCO) can be synchronously reset when PHSTR is asserted. The PHSTR signal passes through the input

FIFO block, using the input clock associated with the clocking mode. If the FIFO is enabled, there can be some

uncertainty in the exact instant the PHSTR synchronization signal arrives at the NCO accumulator due to the

elastic capabilities of the FIFO. For example, in dual-clock mode with the FIFO enabled, the internal clock

generator divides down the CLK2/CLK2C input signal to generate the FIFO output clock. The phase of this

generated clock is unknown externally, resulting in an uncertainty of the exact PHSTR instant of as much as a

few input clock cycles.

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