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align +

CLK2

* 0.5 ns

CLK2

CLK1

DA[15:0]

DB[15:0]

∆ < talign

T0002−01

CLK1

DA[15:0]

DB[15:0]

T0154−01

Interleave Bus Mode

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

3. PLLVDD = 0 V and dual_clk = 1: DUAL CLOCK MODE

In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and the input data

rate through CLK1/CLK1C. There are two options in dual clock mode: with FIFO (inv_plllock set) and without

FIFO (inv_plllock clear). If the FIFO is not used, the CLK1/CLK1C input is used to set the phase of the internal

clock divider. In this case, the edges of CLK1 and CLK2 must be aligned to within ±talign (Figure 47), defined as

where fCLK2 is the clock frequency at CLK2. For example, talign = 0.5 ns at fCLK2 = 500 MHz and 1.5 ns at fCLK2 =

250 MHz.

If the FIFO is enabled (inv_plllock set) in dual clock mode, then CLK1 is only used as an input latch (Figure 48),

is independent from the internal divided clock generated from CLK2/CLK2C, and there is no alignment

specification. However, the FIFO must be synchronized by one of the methods listed in the SYNC_CNTL

between CLK1 and the internally divided clock.

Figure 47. Dual Clock Mode Without FIFO

Figure 48. Dual Clock Mode With FIFO

The CDC7005 from Texas Instruments is recommended for providing phase-aligned clocks at different

frequencies for this application.

In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5687 on data

bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 49 shows

the DAC5687 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 50.

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