W25X05CLZPIG datasheet(28/51 Pages) WINBOND

номер детали	W25X05CLZPIG

подробное описание детали	2.5 / 3 / 3.3 V 512K / 1M / 2M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI

PDF	51 Pages

Scroll/Zoom	100%

производитель	WINBOND [Winbond]

домашняя страница	http://www.winbond.com

Logo

28 / 51 page

W25X05CL/10CL/20CL

Publication Release Date: March 23, 2012

- 28 -

Revision B

8.2.18

Chip Erase (C7h or 60h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A

Write Enable instruction must be executed before the device will accept the Chip Erase Instruction

(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and

shifting the in

struction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 18.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip

Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction

will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in

progress, the Read Status Register instruction may still be accessed to check the status of the BUSY

bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is

ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable

Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed

if any page is protected by the Block Protect (TB, BP1 and BP0) bits (see Status Register Memory

Protection table).

Figure 18. Chip Erase Instruction Sequence Diagram

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (C7h/60h)

High Impedance

Mode 0

Mode 3

W25X05CLZPIG датащи(PDF) 28 Page - Winbond