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W25X05CL/10CL/20CL

Publication Release Date: March 23, 2012

- 21 -

Revision B

8.2.11

Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO

pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to

input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for

code execution (XIP) directly from the Dual SPI in some applications.

Fast Read Dual I/O with “Continuous Read Mode”

The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The

upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the

inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-

0) are don’t

care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out

clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after

/CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 12b.

This reduces the instruction sequence by eight clocks and allows the Read address to be immediately

entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the

next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus

returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset

(M7-0) before issuing normal instructions (See 9.2.12 for detail descriptions).

Figure 12a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4

 10)

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (BBh)

/CS

CLK

(IO

IOs switch from

Input to Output

A23-16

A15-8

A7-0

M7-0

Byte 1

Byte 2

Byte 3

Byte 4

= MSB

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