AM85C30 datasheet(153/194 Pages) AMD

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SCC Application Notes

AMD

7–4

Bits D4–D0 are Mode bits that can be enabled or disabled either by being set to ‘1’ or re-

set to ‘0’. Each Mode bit affects only one function. For example, Bit D1 is the No Vector

mode bit; it controls whether or not the SCC will respond to an interrupt acknowledge cy-

cle by placing a vector on the data bus. If this bit is set, no vector is returned. In Com-

mand bits entry, each new command requires a separate rewrite of the entire register.

Care must be taken when issuing a command so that the Mode bits are not changed acci-

dentally.

7.1.1.2

Initialization Procedure

The SCC initialization procedure is divided into three parts. The first part consists of pro-

gramming the operation modes (e.g., bits-per-character, parity) and loading the constants

(e.g., interrupt vector, time constants). The second part enables the hardware functions

(e.g., transmitter, receiver, baud-rate generator). It is important that the operating modes

are programmed before the hardware functions are enabled. The third part, if required,

consists of enabling the different interrupts.

Table 7–2 shows the order (from top to bottom) in which the SCC registers are to be pro-

grammed. Those registers that need not be programmed are listed as optional in the

comments column. The bits in the registers that are marked with an ‘X’ are to be pro-

grammed by the user. The bits marked with an ‘S’ are to be set to their previous pro-

grammed value. For example, in part 2, Write Register 3, bits D1–D7 are shown with an

‘S’ because they have been programmed in part 1 and must remain set to the same

value.

AM85C30 датащи(PDF) 153 Page - Advanced Micro Devices