AM85C30 datasheet(51/194 Pages) AMD

51 / 194 page

I/O Programming Functional Description

AMD

3–20

3.3.9.4

DMA Request on Receive (Using W/REQ)

The DMA Request on Receive function using the

W/REQ pin is selected by programming

WR1 as shown below.

D6 D5

D4 D3

D2 D1

WR1—DMA Request on Receive Using W/REQ

In this mode, the

W/REQ pin carries the DMA Request signal, which is active Low. When

this mode is selected, but not yet enabled, the

W/REQ pin is driven High. When the en-

able bit is set,

W/REQ will go Low if RR8 contains a character at the time, or will remain

High until a character enters RR8. Note that the

W/REQ pin will follow the state of RR8

even though the receiver is disabled. Thus, if the receiver is disabled but the DMA Re-

quest function is enabled, the DMA will transfer the previously received data correctly. In

this mode the

W/REQ pin directly follows the state of RR8 with only one exception. The

W/REQ pin goes Low when a character enters RR8 and remains Low until this character

is removed from the receive buffer. The SCC generates only one falling edge on

W/REQ

per character transfer requested and the timing for this is shown in Figure 3–10.

The one exception occurs in the case of a special receive condition in the Receive Inter-

rupt on First Character or Special Condition mode, or the Receive Interrupt on Special

Condition Only mode. In these two interrupt modes any receive character with a special

receive condition is locked at the top of the FIFO until an Error Reset command is issued.

This character in the receive FIFO would ordinarily cause additional DMA Requests after

the first time it is read. However, the logic in the SCC guarantees only one falling edge on

W/REQ by holding the W/REQ pin High from the time the character with the special re-

ceive condition is read, and the FIFO locked, until after the Error Reset command has

been issued. Once the FIFO is unlocked by the Error Reset Command,

W/REQ again

follows the state of the receive buffer.

W/REQ will go High in response to the falling edge

RD, but only when the receive buffer in the SCC is accessed. This is shown in Figure

3–11.

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