AM85C30 datasheet(152/194 Pages) AMD

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7–3

SCC Application Notes

CHAPTER 7

7.1

Am8530H INITIALIZATION

7.1.1

Introduction

This application note describes the software initialization procedure for the Am8530 Serial

Communications Controller (SCC).

Table 7–1 provides a worksheet that can be used as an aid when initializing the SCC.

Since all SCC operation modes are initialized in a similar manner, the worksheet can be

used to tailor the SCC device to the user’s individual need. Specific examples are given in

the following chapters.

7.1.1.1

Each of the SCC’s two channels has its own separate Write registers that are pro-

grammed to initialize different operating modes. There are two types of bits in the Write

registers: Command bits and Mode bits. An example of a register that contains both

types of bits is Write Register 9 (WR9), and is shown in Figure 7–1.

WR9 is the Master Interrupt Control register and contains the Reset command bits. Com-

mand bits are denoted by having boxes drawn around them in register diagrams. Bit D5

in this register is not used in this register and must be 0 at all times.

D7 D6 D5 D4 D3 D2 D1 D0

No Reset

Channel Reset B

Channel Reset A

Force Hardware Reset

VIS

DLC

MIE

STATUS HIGH/

STATUS LOW

Figure 7–1. Write Register 9

The Command bits, D7 and D6, select one of the reset commands for the SCC. Setting

either of these bits to 1 disables both the receiver and the transmitter in the correspond-

ing channel, forces TxD for the channel marking, forces the modem control signals High

in that channel, resets all IPs and IUSs, and disables all interrupts in that channel. Func-

tions controlled by the Command bits can be enabled or disabled only; they cannot be

toggled.

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