AM85C30 datasheet(48/194 Pages) AMD

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I/O Programming Functional Description

AMD

3–17

In this mode, the

W/REQ pin carries the Wait signal, and is open-drain when inactive and

Low when active. When the processor attempts to read data from the Receive Data FIFO

and it is empty, the SCC will assert

W/REQ until a character has reached the top of the

FIFO. This allows the use of a block-move instruction to transfer the receive data.

W/REQ

will go active in response to

RD going active, but only if RR8 (Receive Buffer) is being

accessed, either directly or via the pointers. The

W/REQ pin is released in response to

the falling edge of PCLK. Details of the timing are shown in Figure 3–7.

3.9.3

DMA Requests

The two DMA request pins,

W/REQ and DTR/REQ, can be programmed to be used as

DMA requests. The

W/REQ pin can be used as either a transmit or a receive request, but

the

DTR/REQ pin can be used only as a transmit request. Hence, for full-duplex opera-

tion, the

W/REQ pin should be used for receive and the DTR/REQ pin used for transmit.

These modes are described below.

3.9.3.1

DMA Request on Transmit (Using W/REQ)

The DMA Request on Transmit function using the

W/REQ pin is enabled by programming

WR1 as shown below.

D6 D5

D4 D3

D2 D1

WR1—DMA on Transmit Function Selection

ASYNC Modes

SYNC Modes

TRxC

PCLK

WAIT

Figure 3–6. Wait on Transmit Timing

ASYNC Modes

SYNC Modes

RTxC

PCLK

WAIT

5...8

Figure 3–7. Wait on Receive Timing

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