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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM85C30 датащи(PDF) 25 Page - Advanced Micro Devices |
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AM85C30 датащи(HTML) 25 Page - Advanced Micro Devices |
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25 / 194 page  System Interface AMD 2–7 A/ B, D/C INTACK CE WR Address Valid Data Valid D 0 - D 7 10216A-010A Figure 2–2. SCC Write Cycle PCLK D0 – D7 RD INTACK IEI IEO INT Vector Figure 2–3. Interrupt Acknowledge Cycle 2.5 Am85C30 Enhancement Register Access SDLC/HDLC enhancements on the Am85C30 are enabled or disabled via bits D2 and D0 in WR15. Bit D2 determines whether or not the 10x19-bit SDLC/HDLC frame status FIFO is enabled while bit D0 determines whether or not other SDLC/HDLC mode enhance- ments are enabled via WR7’. Table 2–3 shows what functions on the Am85C30 are en- abled when these bits are set. When bit D2 of WR15 is set to ‘1’, two additional registers (RR6 and RR7) per channel specific to the 10x19-bit frame status FIFO are made available. The Am85C30 register map when this function is enabled is shown in Table 2–4. |
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