AM85C30 datasheet(36/194 Pages) AMD

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I/O Programming Functional Description

AMD

3–5

W/DMA

REQ

Enable

W/DMA

REQ

Funct.

W/DMA

REQ on

Rx/Tx

Parity

INT

Enable

INT

Enable

Ext/Sta

INT

Enable

— Rx INT Disable

— Rx INT on 1st Char. or

Special Condition

— INT on All Rx Char. or

Special Condition

— Rx INT on Special Only

WR1—Interrupt Source IE

3.4.2

Interrupt Pending Bit

The Interrupt Pending (IP) bit for a given source of interrupt may be set by the presence

of an interrupt condition in the SCC and is reset directly by the processor, or indirectly by

some action that the processor may take. If the corresponding IE bit is not set, the IP for

that source of interrupt will never be set. The IP bits in the SCC are read-only via RR3 as

shown above.

Ch. A

Ext/Sta

Ch. B

Ext/Sta

RR3—Interrupt Pending

3.4.3

Interrupt Under Service Bit

The Interrupt Under Service (IUS) bits are not observable by the processor. An IUS bit is

set during an Interrupt Acknowledge cycle for the highest-priority IP. The IUS bit is used

to control the operation of internal and external daisy chain interrupts. The internal daisy

chain links the six sources of interrupt in a fixed order, chaining the IUS bits for each

source. While an internal IUS bit is set, all lower-priority interrupt requests are masked

off; during an Interrupt Acknowledge cycle the IP bits are also gated into the daisy chain.

This insures that the highest-priority IP selected will have its IUS bit set. At the end of an

interrupt service routine, the processor must issue a Reset Highest IUS Command in

WR0 to re-enable lower-priority interrupts. This is the only way, short of a software or

hardware reset, that an IUS bit may be reset.

3.4.4

Disable Lower Chain Bit

The Disable Lower Chain (DLC) bit in WR9 (D2) is used to disable all SCCs in a lower

position on the external daisy chain. If this bit is set to ‘1’, the IEO pin is driven Low and

prevents lower-priority devices from generating an interrupt request. Note that the IUS bit,

when set, will have the same effect but is not controllable through software, and the point

where lower-priority interrupts are masked off may not correspond to the chip boundary.

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