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AM85C30 датащи(PDF) 47 Page - Advanced Micro Devices |
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AM85C30 датащи(HTML) 47 Page - Advanced Micro Devices |
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47 / 194 page ![]() I/O Programming Functional Description AMD 3–16 D7 D6 D5 D4 D3 D2 D1 DTR/ REQ Funct. D0 Wait/ DMA REQ Funct. Wait/ DMA REQ Enable Wait/ DMA REQ Rx/Tx D7 D6 D5 D4 D3 D2 D1 D0 WR14 Register Layout WR1 Register Layout Each channel in the SCC has two pins, DTR/REQ and W/REQ, which may be used to control the block transfer of data. Both pins in each channel may be programmed to act as DMA Request signals, and one pin ( W/REQ) in each channel may be programmed to act as a Wait signal for the CPU. In either mode, it is advisable to select and enable the mode in two separate accesses of the appropriate register. The first access should select the mode and the second access should enable the function. This procedure prevents glitches on the output pins. Reset forces Wait mode, with W/REQ open-drain. 3.9.1 Wait on Transmit The Wait function on transmit is selected by programming WR1 as shown below. 10 0? ?? ?? D7 D6 D5 D4 D3 D2 D1 D0 WR1—Wait on Transmit Function Selection In this mode, the W/REQ pin carries the Wait signal, and is open-drain when inactive and Low when active. When the processor attempts to write to WR8 (Transmit Buffer) and it is full, the SCC will assert W/REQ until the buffer is empty. This allows the use of a block- move instruction to transfer the transmit data. W/REQ will go active in response to WR going active but only if WR8 (Transmit Buffer) is being accessed, either directly or via the pointers. The W/REQ pin is released in response to the falling edge of PCLK. Details of the timing are shown in Figure 3–6. 3.9.2 Wait on Receive The Wait function on receive is selected by programming WR1 as shown below. 10 1? ?? ?? D7 D6 D5 D4 D3 D2 D1 D0 WR1—Wait on Receive Function Selection |
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