AM79C976 datasheet(164/309 Pages) AMD

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Am79C976

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P R E L I M INARY

PMAT0: OnNow Pattern Register 0

Offset 190h

This register is used to control and indirectly access the

Pattern Match RAM (PMR). When the PMAT_MODE

bit (CMD7, bit3) is 1, Pattern Match logic is enabled. No

bus accesses into PMR are possible, and PMAT0 and

PMAT1 are ignored. When PMAT_MODE is set, a read

of PMAT0 or PMAT1 returns all undefined bits.

When the PMAT_MODE bit (CMD7, bit3) is 0, the Pat-

tern Match logic is disabled and accesses to the PMR

are possible. Bits 6-0 of PMAT0 specify the address of

the PMR word to be accessed. Following the write to

PMAT0, the PMR word may be read by reading PMAT1

and the high order bytes of PMAT0 in any order. To

write to PMR word, the write to PMAT0 must be fol-

lowed by a write to PMAT1 to complete the operation.

The RAM will not actually be written until the write to

PMAT1 is complete. The write to PMAT1 causes all 5

bytes (two bytes of PMAT1 and the upper three bytes of

PMAT0) to be written to whatever PMR word is ad-

dressed by bits 6:0 of PMAT0.

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 70. PMAT0: OnNow Pattern Register 0

30$72Q1RZ 3DWWHUQ 5HJLVWHU

Offset 194h

This register is used to control and indirectly access the

Pattern Match RAM (PMR). When the PMAT_MODE

bit (CMD7, bit3) is 1, Pattern Match logic is enabled. No

bus accesses into PMR are possible, and PMAT0 and

PMAT1 are ignored. When PMAT_MODE is set, a read

of PMAT0 or PMAT1 returns all undefined bits.

When the PMAT_MODE bit (CMD7, bit3) is 0, the Pat-

tern Match logic is disabled and accesses to the PMR

are possible. Bits 6-0 of PMAT0 specify the address of

the PMR word to be accessed. Following the write to

PMAT0, the PMR word may be read by reading PMAT1

and the high order bytes of PMAT0 in any order. To

write to PMR word, the write to PMAT0 must be fol-

lowed by a write to PMAT1 to complete the operation.

The RAM will not actually be written until the write to

PMAT1 is complete. The write to PMAT1 causes all

5 bytes (two bytes of PMAT1 and the upper three bytes

of PMAT0) to be written to whatever PMR word is ad-

dressed by bits 6:0 of PMAT0.

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 71. PMAT1: OnNow Pattern Register 1

Bit

Name

Description

31-24

PMR_B2

Pattern Match RAM Byte 2. This byte is written into or read from Byte 2 of the Pattern Match RAM.

This field is an alias of BCR46, bits [15:8].

23-16

PMR_B1

Pattern Match RAM Byte 1. This byte is written into or read from Byte 1 of the Pattern Match RAM.

This field is an alias of BCR46, bits [7:0].

15-8

PMR_B0

Pattern Match RAM Byte 0. This byte is written into or read from Byte 0 of the Pattern Match RAM.

This field is an alias of BCR45, bits [15:8].

RES

Reserved location. Written as zero and read as undefined.

6-0

PMR_ADDR

Pattern Match RAM Address. These bits are the Pattern Match RAM address to be written to or

read from.

Bit

Name

Description

15-8

PMR_B4

Pattern Match RAM Byte 4. This byte is written into or read from Byte 4 of the Pattern Match RAM.

This field is an alias of BCR47, bits [15:8].

7-0

PMR_B3

Pattern Match RAM Byte 3. This byte is written into or read from Byte 3 of the Pattern Match RAM.

This field is an alias of BCR47, bits [7:0].

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