AM79C976 datasheet(168/309 Pages) AMD

168 / 309 page

168

Am79C976

8/01/00

P R E L I M INARY

STAT0: Status0

Offset 030h

STAT0 indicates the status of various Am79C976 func-

tions. All bits in this register except for bits 12:10 indi-

cate current status and are read only. Bits 12:10 are

latches that indicate the cause of a wake-up event.

These three bits are cleared to 0 when power is first ap-

plied to the device (power-on reset), but they are not af-

fected by the state of the RST pin so that they are not

disturbed when PCI bus power is removed and reap-

plied. Bits 12:10 are “write 1 to clear”. Therefore, the

CPU can clear bits 12:10 by reading the register and

then writing back the same data that it read.

Table 78. STAT0: Status0 Register

Bit

Name

Description

31-15

RES

Reserved locations. Written as zeros and read as undefined.

PAUSE_PEND

Pause Pending. This bit is set to 1 during the interval between the time that the Am79C976 device

receives a command to transmit a MAC Control Pause frame and the time that the device finishes

transmitting the frame. The host CPU should not attempt to write to the Pause Length Register

while this bit is 1.

This bit is read only and is cleared by H_RESET.

PAUSING

Pausing. This bit indicates that the device has received a MAC Control Pause frame, and the pause

timer has not yet timed out.

This bit is read only and is cleared by H_RESET.

PMAT_DET

Pattern Match Detected. This bit indicates that an OnNow pattern match has occurred while the

Am79C976 device was in the OnNow pattern match mode.

This bit is an alias of PMAT in CSR116.

This bit can be cleared to 0 either by writing 0 to CSR116, bit 7, or by writing 1 to STAT0, bit 12.

This bit is cleared to 0 when power is first applied to the device, but not by the assertion of RST.

MP_DET

Magic Packet Frame Detected. This bit indicates that a Magic Packet pattern match has occurred

while the Am79C976 device was in the Magic Packet mode.

This bit is an alias of MPMAT in CSR116.

This bit can be cleared to 0 either by writing 0 to CSR116, bit 5, or by writing 1 to STAT0, bit 11.

This bit is cleared to 0 when power is first applied to the device, but not by the assertion of RST.

LC_DET

Link Change Detected. This bit indicates that a change in the link status of the external PHY device

has been detected while the device was in the Link Change Wake-up mode.

This bit is an alias of LCDET in CSR116.

This bit can be cleared to 0 either by writing 1 to CSR116, bit 9, or by writing 1 to STAT0, bit 10.

This bit is cleared to 0 when power is first applied to the device, but not by the assertion of RST.

9-7

SPEED

Speed. This field indicates the bit rate at which the network is running. The following encoding is

used:

000 Unknown

001 Reserved

010 10 Mb/s

011 100 Mb/s

100-111 Reserved

These bits are read only and are cleared by H_RESET.

FULL_DPLX

Full Duplex. This bit is set when the device is operating in full-duplex mode.

This bit is read only and is cleared by H_RESET.

AM79C976 датащи(PDF) 168 Page - Advanced Micro Devices

AM79C976 датащи(HTML) 168 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL