AM79C976 datasheet(161/309 Pages) AMD

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Am79C976

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P R E L I M INARY

Table 66. PADR: Physical Address Register

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Offset 0DEh

All bits in this register are cleared to 0 when the RST

pin is asserted, before the serial EEPROM is read, and

after a serial EEPROM read error. This register is read-

only.

Table 67. PAUSE_CNT: Pause Count Register

3&,'$7$3&, '$7$ 5HJLVWHU=HUR$OLDV5HJLVWHU

Offset 1BCh

This register contains the data that appears in the

DATA_SCALE field of the PCI Power Management

Control/Status Register (PMCSR) and the PCI Data

0. Since the DATA_SCALE and DATA fields in the con-

figuration space are read only, this register provides a

means of programming them indirectly, normally by

loading them from the serial EEPROM.

This register is an alias of BCR37.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 68. PCIDATA0: PCI DATA Register Zero Alias Register

3&,'$7$3&, '$7$ 5HJLVWHU2QH$OLDV 5HJLVWHU

Offset 1BEh

This register is identical to the PCI Data Register Zero

Alias Register except that it contains the data that ap-

pears in the DATA_SCALE field of the PCI Power Man-

agement Control/Status Register (PMCSR) and the

PCI Data Register when the DATA_SEL field of

PMCSR is set to 1.

Bit

Name

Description

47-0

PADR

MAC Physical Address, PADR[47:0]. This register contains 48-bit, globally unique station address

assigned to this device. If the least significant bit of the first byte of a received frame is 0, the

destination address of the frame is a unicast address, which will be compared with the contents of

the PADR. If this bit is 0 and the frame’s destination address exactly matches the contents of PADR,

the frame is accepted and copied into the host system memory.

The byte order is such that PADR7[7:0] corresponds to the first address byte transferred over the

network.

Unicast address matching can be disabled by setting the Disable Receive Physical Address bit

(DCRVPA, bit 18 in CMD2). If DRCVPA is set to 1, a match of a frame’s destination address with

the contents of PADR will not cause the frame to be accepted and copied into the host memory.

The contents of this register should be loaded from EEPROM.

This register can also be loaded from the initialization block after the INIT bit in CSR0 has been set.

This register is an alias for CSR12, CSR13, and CSR14.

Bit

Name

Description

31-16

RES

Reserved locations. Written as zeros and read as undefined

15-0

PAUSE_CNT

Pause Count. This field indicates the pause time parameter that was contained in the

request_operand field of the most recently received MAC Control Pause frame.

Bit

Name

Description

15-10

RES

Reserved locations. Written as zeros and read as undefined.

9-8

D0_SCALE

These bits correspond to the DATA_SCALE field of the PMCSR (offset Register 44 of the PCI

configuration space, bits 14-13). Refer to the description of DATA_SCALE for the meaning of this

field.

7-0

DATA0

These bits correspond to the PCI DATA register (offset Register 47 of the PCI configuration space,

bits 7-0). Refer to the description of DATA register for the meaning of this field.

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